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Richard Zhubjorn-helgaas
Richard Zhu
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bjorn-helgaas
committed
PCI: imx6: Use devm_clk_bulk_get_all() to fetch clocks
Use devm_clk_bulk_get_all() helper to simplify clock handle code. No functional changes intended. Signed-off-by: Richard Zhu <[email protected]> [kwilczynski: commit log, refactor to use dev_err_probe()] Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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‎drivers/pci/controller/dwc/pci-imx6.c

Lines changed: 14 additions & 61 deletions
Original file line numberDiff line numberDiff line change
@@ -108,7 +108,6 @@ enum imx_pcie_variants {
108108

109109
#define imx_check_flag(pci, val) (pci->drvdata->flags & val)
110110

111-
#define IMX_PCIE_MAX_CLKS 6
112111
#define IMX_PCIE_MAX_INSTANCES 2
113112

114113
struct imx_pcie;
@@ -119,9 +118,6 @@ struct imx_pcie_drvdata {
119118
u32 flags;
120119
int dbi_length;
121120
const char *gpr;
122-
const char * const *clk_names;
123-
const u32 clks_cnt;
124-
const u32 clks_optional_cnt;
125121
const u32 ltssm_off;
126122
const u32 ltssm_mask;
127123
const u32 mode_off[IMX_PCIE_MAX_INSTANCES];
@@ -136,7 +132,8 @@ struct imx_pcie_drvdata {
136132
struct imx_pcie {
137133
struct dw_pcie *pci;
138134
struct gpio_desc *reset_gpiod;
139-
struct clk_bulk_data clks[IMX_PCIE_MAX_CLKS];
135+
struct clk_bulk_data *clks;
136+
int num_clks;
140137
struct regmap *iomuxc_gpr;
141138
u16 msi_ctrl;
142139
u32 controller_id;
@@ -469,13 +466,14 @@ static int imx_setup_phy_mpll(struct imx_pcie *imx_pcie)
469466
int mult, div;
470467
u16 val;
471468
int i;
469+
struct clk_bulk_data *clks = imx_pcie->clks;
472470

473471
if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_IMX_PHY))
474472
return 0;
475473

476-
for (i = 0; i < imx_pcie->drvdata->clks_cnt; i++)
477-
if (strncmp(imx_pcie->clks[i].id, "pcie_phy", 8) == 0)
478-
phy_rate = clk_get_rate(imx_pcie->clks[i].clk);
474+
for (i = 0; i < imx_pcie->num_clks; i++)
475+
if (strncmp(clks[i].id, "pcie_phy", 8) == 0)
476+
phy_rate = clk_get_rate(clks[i].clk);
479477

480478
switch (phy_rate) {
481479
case 125000000:
@@ -667,7 +665,7 @@ static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie)
667665
struct device *dev = pci->dev;
668666
int ret;
669667

670-
ret = clk_bulk_prepare_enable(imx_pcie->drvdata->clks_cnt, imx_pcie->clks);
668+
ret = clk_bulk_prepare_enable(imx_pcie->num_clks, imx_pcie->clks);
671669
if (ret)
672670
return ret;
673671

@@ -684,7 +682,7 @@ static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie)
684682
return 0;
685683

686684
err_ref_clk:
687-
clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks);
685+
clk_bulk_disable_unprepare(imx_pcie->num_clks, imx_pcie->clks);
688686

689687
return ret;
690688
}
@@ -693,7 +691,7 @@ static void imx_pcie_clk_disable(struct imx_pcie *imx_pcie)
693691
{
694692
if (imx_pcie->drvdata->enable_ref_clk)
695693
imx_pcie->drvdata->enable_ref_clk(imx_pcie, false);
696-
clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks);
694+
clk_bulk_disable_unprepare(imx_pcie->num_clks, imx_pcie->clks);
697695
}
698696

699697
static int imx6sx_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
@@ -1474,7 +1472,7 @@ static int imx_pcie_probe(struct platform_device *pdev)
14741472
struct imx_pcie *imx_pcie;
14751473
struct device_node *np;
14761474
struct device_node *node = dev->of_node;
1477-
int i, ret, req_cnt, domain;
1475+
int ret, domain;
14781476
u16 val;
14791477

14801478
imx_pcie = devm_kzalloc(dev, sizeof(*imx_pcie), GFP_KERNEL);
@@ -1520,20 +1518,11 @@ static int imx_pcie_probe(struct platform_device *pdev)
15201518
"unable to get reset gpio\n");
15211519
gpiod_set_consumer_name(imx_pcie->reset_gpiod, "PCIe reset");
15221520

1523-
if (imx_pcie->drvdata->clks_cnt >= IMX_PCIE_MAX_CLKS)
1524-
return dev_err_probe(dev, -ENOMEM, "clks_cnt is too big\n");
1525-
1526-
for (i = 0; i < imx_pcie->drvdata->clks_cnt; i++)
1527-
imx_pcie->clks[i].id = imx_pcie->drvdata->clk_names[i];
1528-
15291521
/* Fetch clocks */
1530-
req_cnt = imx_pcie->drvdata->clks_cnt - imx_pcie->drvdata->clks_optional_cnt;
1531-
ret = devm_clk_bulk_get(dev, req_cnt, imx_pcie->clks);
1532-
if (ret)
1533-
return ret;
1534-
imx_pcie->clks[req_cnt].clk = devm_clk_get_optional(dev, "ref");
1535-
if (IS_ERR(imx_pcie->clks[req_cnt].clk))
1536-
return PTR_ERR(imx_pcie->clks[req_cnt].clk);
1522+
imx_pcie->num_clks = devm_clk_bulk_get_all(dev, &imx_pcie->clks);
1523+
if (imx_pcie->num_clks < 0)
1524+
return dev_err_probe(dev, imx_pcie->num_clks,
1525+
"failed to get clocks\n");
15371526

15381527
if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_PHYDRV)) {
15391528
imx_pcie->phy = devm_phy_get(dev, "pcie-phy");
@@ -1672,13 +1661,6 @@ static void imx_pcie_shutdown(struct platform_device *pdev)
16721661
imx_pcie_assert_core_reset(imx_pcie);
16731662
}
16741663

1675-
static const char * const imx6q_clks[] = {"pcie_bus", "pcie", "pcie_phy"};
1676-
static const char * const imx8mm_clks[] = {"pcie_bus", "pcie", "pcie_aux"};
1677-
static const char * const imx8mq_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"};
1678-
static const char * const imx6sx_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_inbound_axi"};
1679-
static const char * const imx8q_clks[] = {"mstr", "slv", "dbi"};
1680-
static const char * const imx95_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux", "ref"};
1681-
16821664
static const struct imx_pcie_drvdata drvdata[] = {
16831665
[IMX6Q] = {
16841666
.variant = IMX6Q,
@@ -1688,8 +1670,6 @@ static const struct imx_pcie_drvdata drvdata[] = {
16881670
IMX_PCIE_FLAG_SUPPORTS_SUSPEND,
16891671
.dbi_length = 0x200,
16901672
.gpr = "fsl,imx6q-iomuxc-gpr",
1691-
.clk_names = imx6q_clks,
1692-
.clks_cnt = ARRAY_SIZE(imx6q_clks),
16931673
.ltssm_off = IOMUXC_GPR12,
16941674
.ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2,
16951675
.mode_off[0] = IOMUXC_GPR12,
@@ -1704,8 +1684,6 @@ static const struct imx_pcie_drvdata drvdata[] = {
17041684
IMX_PCIE_FLAG_IMX_SPEED_CHANGE |
17051685
IMX_PCIE_FLAG_SUPPORTS_SUSPEND,
17061686
.gpr = "fsl,imx6q-iomuxc-gpr",
1707-
.clk_names = imx6sx_clks,
1708-
.clks_cnt = ARRAY_SIZE(imx6sx_clks),
17091687
.ltssm_off = IOMUXC_GPR12,
17101688
.ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2,
17111689
.mode_off[0] = IOMUXC_GPR12,
@@ -1722,8 +1700,6 @@ static const struct imx_pcie_drvdata drvdata[] = {
17221700
IMX_PCIE_FLAG_SUPPORTS_SUSPEND,
17231701
.dbi_length = 0x200,
17241702
.gpr = "fsl,imx6q-iomuxc-gpr",
1725-
.clk_names = imx6q_clks,
1726-
.clks_cnt = ARRAY_SIZE(imx6q_clks),
17271703
.ltssm_off = IOMUXC_GPR12,
17281704
.ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2,
17291705
.mode_off[0] = IOMUXC_GPR12,
@@ -1739,8 +1715,6 @@ static const struct imx_pcie_drvdata drvdata[] = {
17391715
IMX_PCIE_FLAG_HAS_APP_RESET |
17401716
IMX_PCIE_FLAG_HAS_PHY_RESET,
17411717
.gpr = "fsl,imx7d-iomuxc-gpr",
1742-
.clk_names = imx6q_clks,
1743-
.clks_cnt = ARRAY_SIZE(imx6q_clks),
17441718
.mode_off[0] = IOMUXC_GPR12,
17451719
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
17461720
.enable_ref_clk = imx7d_pcie_enable_ref_clk,
@@ -1752,8 +1726,6 @@ static const struct imx_pcie_drvdata drvdata[] = {
17521726
IMX_PCIE_FLAG_HAS_PHY_RESET |
17531727
IMX_PCIE_FLAG_SUPPORTS_SUSPEND,
17541728
.gpr = "fsl,imx8mq-iomuxc-gpr",
1755-
.clk_names = imx8mq_clks,
1756-
.clks_cnt = ARRAY_SIZE(imx8mq_clks),
17571729
.mode_off[0] = IOMUXC_GPR12,
17581730
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
17591731
.mode_off[1] = IOMUXC_GPR12,
@@ -1767,8 +1739,6 @@ static const struct imx_pcie_drvdata drvdata[] = {
17671739
IMX_PCIE_FLAG_HAS_PHYDRV |
17681740
IMX_PCIE_FLAG_HAS_APP_RESET,
17691741
.gpr = "fsl,imx8mm-iomuxc-gpr",
1770-
.clk_names = imx8mm_clks,
1771-
.clks_cnt = ARRAY_SIZE(imx8mm_clks),
17721742
.mode_off[0] = IOMUXC_GPR12,
17731743
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
17741744
.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
@@ -1779,8 +1749,6 @@ static const struct imx_pcie_drvdata drvdata[] = {
17791749
IMX_PCIE_FLAG_HAS_PHYDRV |
17801750
IMX_PCIE_FLAG_HAS_APP_RESET,
17811751
.gpr = "fsl,imx8mp-iomuxc-gpr",
1782-
.clk_names = imx8mm_clks,
1783-
.clks_cnt = ARRAY_SIZE(imx8mm_clks),
17841752
.mode_off[0] = IOMUXC_GPR12,
17851753
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
17861754
.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
@@ -1790,17 +1758,12 @@ static const struct imx_pcie_drvdata drvdata[] = {
17901758
.flags = IMX_PCIE_FLAG_HAS_PHYDRV |
17911759
IMX_PCIE_FLAG_CPU_ADDR_FIXUP |
17921760
IMX_PCIE_FLAG_SUPPORTS_SUSPEND,
1793-
.clk_names = imx8q_clks,
1794-
.clks_cnt = ARRAY_SIZE(imx8q_clks),
17951761
},
17961762
[IMX95] = {
17971763
.variant = IMX95,
17981764
.flags = IMX_PCIE_FLAG_HAS_SERDES |
17991765
IMX_PCIE_FLAG_HAS_LUT |
18001766
IMX_PCIE_FLAG_SUPPORTS_SUSPEND,
1801-
.clk_names = imx95_clks,
1802-
.clks_cnt = ARRAY_SIZE(imx95_clks),
1803-
.clks_optional_cnt = 1,
18041767
.ltssm_off = IMX95_PE0_GEN_CTRL_3,
18051768
.ltssm_mask = IMX95_PCIE_LTSSM_EN,
18061769
.mode_off[0] = IMX95_PE0_GEN_CTRL_1,
@@ -1813,8 +1776,6 @@ static const struct imx_pcie_drvdata drvdata[] = {
18131776
IMX_PCIE_FLAG_HAS_PHY_RESET,
18141777
.mode = DW_PCIE_EP_TYPE,
18151778
.gpr = "fsl,imx8mq-iomuxc-gpr",
1816-
.clk_names = imx8mq_clks,
1817-
.clks_cnt = ARRAY_SIZE(imx8mq_clks),
18181779
.mode_off[0] = IOMUXC_GPR12,
18191780
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
18201781
.mode_off[1] = IOMUXC_GPR12,
@@ -1829,8 +1790,6 @@ static const struct imx_pcie_drvdata drvdata[] = {
18291790
IMX_PCIE_FLAG_HAS_PHYDRV,
18301791
.mode = DW_PCIE_EP_TYPE,
18311792
.gpr = "fsl,imx8mm-iomuxc-gpr",
1832-
.clk_names = imx8mm_clks,
1833-
.clks_cnt = ARRAY_SIZE(imx8mm_clks),
18341793
.mode_off[0] = IOMUXC_GPR12,
18351794
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
18361795
.epc_features = &imx8m_pcie_epc_features,
@@ -1842,8 +1801,6 @@ static const struct imx_pcie_drvdata drvdata[] = {
18421801
IMX_PCIE_FLAG_HAS_PHYDRV,
18431802
.mode = DW_PCIE_EP_TYPE,
18441803
.gpr = "fsl,imx8mp-iomuxc-gpr",
1845-
.clk_names = imx8mm_clks,
1846-
.clks_cnt = ARRAY_SIZE(imx8mm_clks),
18471804
.mode_off[0] = IOMUXC_GPR12,
18481805
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
18491806
.epc_features = &imx8m_pcie_epc_features,
@@ -1854,15 +1811,11 @@ static const struct imx_pcie_drvdata drvdata[] = {
18541811
.flags = IMX_PCIE_FLAG_HAS_PHYDRV,
18551812
.mode = DW_PCIE_EP_TYPE,
18561813
.epc_features = &imx8q_pcie_epc_features,
1857-
.clk_names = imx8q_clks,
1858-
.clks_cnt = ARRAY_SIZE(imx8q_clks),
18591814
},
18601815
[IMX95_EP] = {
18611816
.variant = IMX95_EP,
18621817
.flags = IMX_PCIE_FLAG_HAS_SERDES |
18631818
IMX_PCIE_FLAG_SUPPORT_64BIT,
1864-
.clk_names = imx8mq_clks,
1865-
.clks_cnt = ARRAY_SIZE(imx8mq_clks),
18661819
.ltssm_off = IMX95_PE0_GEN_CTRL_3,
18671820
.ltssm_mask = IMX95_PCIE_LTSSM_EN,
18681821
.mode_off[0] = IMX95_PE0_GEN_CTRL_1,

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