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Tomas Winklergregkh
Tomas Winkler
authored and
gregkh
committed
mei: me: disable mei interface on Mehlow server platforms
For SPS firmware versions 5.0 and newer the way detection has changed. The detection is done now via PCI_CFG_HFS_3 register. To prevent conflict the previous method will get sps_4 suffix Disable both CNP_H and CNP_H_3 interfaces. CNP_H_3 requires a separate configuration as it doesn't support DMA. Cc: <[email protected]> Signed-off-by: Tomas Winkler <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
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-18
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4 files changed

+73
-18
lines changed

‎drivers/misc/mei/hw-me-regs.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -107,6 +107,8 @@
107107
# define PCI_CFG_HFS_1_D0I3_MSK 0x80000000
108108
#define PCI_CFG_HFS_2 0x48
109109
#define PCI_CFG_HFS_3 0x60
110+
# define PCI_CFG_HFS_3_FW_SKU_MSK 0x00000070
111+
# define PCI_CFG_HFS_3_FW_SKU_SPS 0x00000060
110112
#define PCI_CFG_HFS_4 0x64
111113
#define PCI_CFG_HFS_5 0x68
112114
#define PCI_CFG_HFS_6 0x6C

‎drivers/misc/mei/hw-me.c

Lines changed: 54 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1366,7 +1366,7 @@ static bool mei_me_fw_type_nm(struct pci_dev *pdev)
13661366
#define MEI_CFG_FW_NM \
13671367
.quirk_probe = mei_me_fw_type_nm
13681368

1369-
static bool mei_me_fw_type_sps(struct pci_dev *pdev)
1369+
static bool mei_me_fw_type_sps_4(struct pci_dev *pdev)
13701370
{
13711371
u32 reg;
13721372
unsigned int devfn;
@@ -1382,7 +1382,36 @@ static bool mei_me_fw_type_sps(struct pci_dev *pdev)
13821382
return (reg & 0xf0000) == 0xf0000;
13831383
}
13841384

1385-
#define MEI_CFG_FW_SPS \
1385+
#define MEI_CFG_FW_SPS_4 \
1386+
.quirk_probe = mei_me_fw_type_sps_4
1387+
1388+
/**
1389+
* mei_me_fw_sku_sps() - check for sps sku
1390+
*
1391+
* Read ME FW Status register to check for SPS Firmware.
1392+
* The SPS FW is only signaled in pci function 0
1393+
*
1394+
* @pdev: pci device
1395+
*
1396+
* Return: true in case of SPS firmware
1397+
*/
1398+
static bool mei_me_fw_type_sps(struct pci_dev *pdev)
1399+
{
1400+
u32 reg;
1401+
u32 fw_type;
1402+
unsigned int devfn;
1403+
1404+
devfn = PCI_DEVFN(PCI_SLOT(pdev->devfn), 0);
1405+
pci_bus_read_config_dword(pdev->bus, devfn, PCI_CFG_HFS_3, &reg);
1406+
trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_3", PCI_CFG_HFS_3, reg);
1407+
fw_type = (reg & PCI_CFG_HFS_3_FW_SKU_MSK);
1408+
1409+
dev_dbg(&pdev->dev, "fw type is %d\n", fw_type);
1410+
1411+
return fw_type == PCI_CFG_HFS_3_FW_SKU_SPS;
1412+
}
1413+
1414+
#define MEI_CFG_FW_SPS \
13861415
.quirk_probe = mei_me_fw_type_sps
13871416

13881417
#define MEI_CFG_FW_VER_SUPP \
@@ -1452,10 +1481,17 @@ static const struct mei_cfg mei_me_pch8_cfg = {
14521481
};
14531482

14541483
/* PCH8 Lynx Point with quirk for SPS Firmware exclusion */
1455-
static const struct mei_cfg mei_me_pch8_sps_cfg = {
1484+
static const struct mei_cfg mei_me_pch8_sps_4_cfg = {
14561485
MEI_CFG_PCH8_HFS,
14571486
MEI_CFG_FW_VER_SUPP,
1458-
MEI_CFG_FW_SPS,
1487+
MEI_CFG_FW_SPS_4,
1488+
};
1489+
1490+
/* LBG with quirk for SPS (4.0) Firmware exclusion */
1491+
static const struct mei_cfg mei_me_pch12_sps_4_cfg = {
1492+
MEI_CFG_PCH8_HFS,
1493+
MEI_CFG_FW_VER_SUPP,
1494+
MEI_CFG_FW_SPS_4,
14591495
};
14601496

14611497
/* Cannon Lake and newer devices */
@@ -1465,8 +1501,18 @@ static const struct mei_cfg mei_me_pch12_cfg = {
14651501
MEI_CFG_DMA_128,
14661502
};
14671503

1468-
/* LBG with quirk for SPS Firmware exclusion */
1504+
/* Cannon Lake with quirk for SPS 5.0 and newer Firmware exclusion */
14691505
static const struct mei_cfg mei_me_pch12_sps_cfg = {
1506+
MEI_CFG_PCH8_HFS,
1507+
MEI_CFG_FW_VER_SUPP,
1508+
MEI_CFG_DMA_128,
1509+
MEI_CFG_FW_SPS,
1510+
};
1511+
1512+
/* Cannon Lake with quirk for SPS 5.0 and newer Firmware exclusion
1513+
* w/o DMA support
1514+
*/
1515+
static const struct mei_cfg mei_me_pch12_nodma_sps_cfg = {
14701516
MEI_CFG_PCH8_HFS,
14711517
MEI_CFG_FW_VER_SUPP,
14721518
MEI_CFG_FW_SPS,
@@ -1492,9 +1538,11 @@ static const struct mei_cfg *const mei_cfg_list[] = {
14921538
[MEI_ME_PCH7_CFG] = &mei_me_pch7_cfg,
14931539
[MEI_ME_PCH_CPT_PBG_CFG] = &mei_me_pch_cpt_pbg_cfg,
14941540
[MEI_ME_PCH8_CFG] = &mei_me_pch8_cfg,
1495-
[MEI_ME_PCH8_SPS_CFG] = &mei_me_pch8_sps_cfg,
1541+
[MEI_ME_PCH8_SPS_4_CFG] = &mei_me_pch8_sps_4_cfg,
14961542
[MEI_ME_PCH12_CFG] = &mei_me_pch12_cfg,
1543+
[MEI_ME_PCH12_SPS_4_CFG] = &mei_me_pch12_sps_4_cfg,
14971544
[MEI_ME_PCH12_SPS_CFG] = &mei_me_pch12_sps_cfg,
1545+
[MEI_ME_PCH12_SPS_NODMA_CFG] = &mei_me_pch12_nodma_sps_cfg,
14981546
[MEI_ME_PCH15_CFG] = &mei_me_pch15_cfg,
14991547
};
15001548

‎drivers/misc/mei/hw-me.h

Lines changed: 9 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/* SPDX-License-Identifier: GPL-2.0 */
22
/*
3-
* Copyright (c) 2012-2019, Intel Corporation. All rights reserved.
3+
* Copyright (c) 2012-2020, Intel Corporation. All rights reserved.
44
* Intel Management Engine Interface (Intel MEI) Linux driver
55
*/
66

@@ -76,11 +76,14 @@ struct mei_me_hw {
7676
* with quirk for Node Manager exclusion.
7777
* @MEI_ME_PCH8_CFG: Platform Controller Hub Gen8 and newer
7878
* client platforms.
79-
* @MEI_ME_PCH8_SPS_CFG: Platform Controller Hub Gen8 and newer
79+
* @MEI_ME_PCH8_SPS_4_CFG: Platform Controller Hub Gen8 and newer
8080
* servers platforms with quirk for
8181
* SPS firmware exclusion.
8282
* @MEI_ME_PCH12_CFG: Platform Controller Hub Gen12 and newer
83-
* @MEI_ME_PCH12_SPS_CFG: Platform Controller Hub Gen12 and newer
83+
* @MEI_ME_PCH12_SPS_4_CFG:Platform Controller Hub Gen12 up to 4.0
84+
* servers platforms with quirk for
85+
* SPS firmware exclusion.
86+
* @MEI_ME_PCH12_SPS_CFG: Platform Controller Hub Gen12 5.0 and newer
8487
* servers platforms with quirk for
8588
* SPS firmware exclusion.
8689
* @MEI_ME_PCH15_CFG: Platform Controller Hub Gen15 and newer
@@ -94,9 +97,11 @@ enum mei_cfg_idx {
9497
MEI_ME_PCH7_CFG,
9598
MEI_ME_PCH_CPT_PBG_CFG,
9699
MEI_ME_PCH8_CFG,
97-
MEI_ME_PCH8_SPS_CFG,
100+
MEI_ME_PCH8_SPS_4_CFG,
98101
MEI_ME_PCH12_CFG,
102+
MEI_ME_PCH12_SPS_4_CFG,
99103
MEI_ME_PCH12_SPS_CFG,
104+
MEI_ME_PCH12_SPS_NODMA_CFG,
100105
MEI_ME_PCH15_CFG,
101106
MEI_ME_NUM_CFG,
102107
};

‎drivers/misc/mei/pci-me.c

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -59,18 +59,18 @@ static const struct pci_device_id mei_me_pci_tbl[] = {
5959
{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)},
6060
{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)},
6161
{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)},
62-
{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_CFG)},
63-
{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_CFG)},
62+
{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_4_CFG)},
63+
{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_4_CFG)},
6464
{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)},
65-
{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_CFG)},
65+
{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_4_CFG)},
6666
{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)},
6767
{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)},
6868

6969
{MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)},
7070
{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)},
71-
{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_CFG)},
72-
{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_CFG)},
73-
{MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_SPS_CFG)},
71+
{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_4_CFG)},
72+
{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_4_CFG)},
73+
{MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_SPS_4_CFG)},
7474

7575
{MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)},
7676
{MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)},
@@ -84,8 +84,8 @@ static const struct pci_device_id mei_me_pci_tbl[] = {
8484

8585
{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)},
8686
{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_3, MEI_ME_PCH8_CFG)},
87-
{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_CFG)},
88-
{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3, MEI_ME_PCH8_CFG)},
87+
{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_SPS_CFG)},
88+
{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3, MEI_ME_PCH12_SPS_NODMA_CFG)},
8989

9090
{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)},
9191
{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_CFG)},

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