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Wolfram SangAndi Shyti
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i2c: uniphier-f: reword according to newest specification
Change the wording of this driver wrt. the newest I2C v7 and SMBus 3.2 specifications and replace "master/slave" with more appropriate terms. Signed-off-by: Wolfram Sang <[email protected]> Reviewed-by: Andi Shyti <[email protected]> Signed-off-by: Andi Shyti <[email protected]>
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drivers/i2c/busses/i2c-uniphier-f.c

Lines changed: 12 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -12,15 +12,15 @@
1212
#include <linux/platform_device.h>
1313

1414
#define UNIPHIER_FI2C_CR 0x00 /* control register */
15-
#define UNIPHIER_FI2C_CR_MST BIT(3) /* master mode */
15+
#define UNIPHIER_FI2C_CR_MST BIT(3) /* controller mode */
1616
#define UNIPHIER_FI2C_CR_STA BIT(2) /* start condition */
1717
#define UNIPHIER_FI2C_CR_STO BIT(1) /* stop condition */
1818
#define UNIPHIER_FI2C_CR_NACK BIT(0) /* do not return ACK */
1919
#define UNIPHIER_FI2C_DTTX 0x04 /* TX FIFO */
20-
#define UNIPHIER_FI2C_DTTX_CMD BIT(8) /* send command (slave addr) */
20+
#define UNIPHIER_FI2C_DTTX_CMD BIT(8) /* send command (target addr) */
2121
#define UNIPHIER_FI2C_DTTX_RD BIT(0) /* read transaction */
2222
#define UNIPHIER_FI2C_DTRX 0x04 /* RX FIFO */
23-
#define UNIPHIER_FI2C_SLAD 0x0c /* slave address */
23+
#define UNIPHIER_FI2C_SLAD 0x0c /* target address */
2424
#define UNIPHIER_FI2C_CYC 0x10 /* clock cycle control */
2525
#define UNIPHIER_FI2C_LCTL 0x14 /* clock low period control */
2626
#define UNIPHIER_FI2C_SSUT 0x18 /* restart/stop setup time control */
@@ -96,7 +96,7 @@ static void uniphier_fi2c_fill_txfifo(struct uniphier_fi2c_priv *priv,
9696
int fifo_space = UNIPHIER_FI2C_FIFO_SIZE;
9797

9898
/*
99-
* TX-FIFO stores slave address in it for the first access.
99+
* TX-FIFO stores target address in it for the first access.
100100
* Decrement the counter.
101101
*/
102102
if (first)
@@ -252,7 +252,7 @@ static void uniphier_fi2c_tx_init(struct uniphier_fi2c_priv *priv, u16 addr,
252252

253253
/* do not use TX byte counter */
254254
writel(0, priv->membase + UNIPHIER_FI2C_TBC);
255-
/* set slave address */
255+
/* set target address */
256256
writel(UNIPHIER_FI2C_DTTX_CMD | addr << 1,
257257
priv->membase + UNIPHIER_FI2C_DTTX);
258258
/*
@@ -288,7 +288,7 @@ static void uniphier_fi2c_rx_init(struct uniphier_fi2c_priv *priv, u16 addr)
288288

289289
uniphier_fi2c_set_irqs(priv);
290290

291-
/* set slave address with RD bit */
291+
/* set target address with RD bit */
292292
writel(UNIPHIER_FI2C_DTTX_CMD | UNIPHIER_FI2C_DTTX_RD | addr << 1,
293293
priv->membase + UNIPHIER_FI2C_DTTX);
294294
}
@@ -310,9 +310,8 @@ static void uniphier_fi2c_recover(struct uniphier_fi2c_priv *priv)
310310
i2c_recover_bus(&priv->adap);
311311
}
312312

313-
static int uniphier_fi2c_master_xfer_one(struct i2c_adapter *adap,
314-
struct i2c_msg *msg, bool repeat,
315-
bool stop)
313+
static int uniphier_fi2c_xfer_one(struct i2c_adapter *adap, struct i2c_msg *msg,
314+
bool repeat, bool stop)
316315
{
317316
struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
318317
bool is_read = msg->flags & I2C_M_RD;
@@ -340,7 +339,7 @@ static int uniphier_fi2c_master_xfer_one(struct i2c_adapter *adap,
340339
uniphier_fi2c_tx_init(priv, msg->addr, repeat);
341340

342341
/*
343-
* For a repeated START condition, writing a slave address to the FIFO
342+
* For a repeated START condition, writing a target address to the FIFO
344343
* kicks the controller. So, the UNIPHIER_FI2C_CR register should be
345344
* written only for a non-repeated START condition.
346345
*/
@@ -403,8 +402,7 @@ static int uniphier_fi2c_check_bus_busy(struct i2c_adapter *adap)
403402
return 0;
404403
}
405404

406-
static int uniphier_fi2c_master_xfer(struct i2c_adapter *adap,
407-
struct i2c_msg *msgs, int num)
405+
static int uniphier_fi2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
408406
{
409407
struct i2c_msg *msg, *emsg = msgs + num;
410408
bool repeat = false;
@@ -418,7 +416,7 @@ static int uniphier_fi2c_master_xfer(struct i2c_adapter *adap,
418416
/* Emit STOP if it is the last message or I2C_M_STOP is set. */
419417
bool stop = (msg + 1 == emsg) || (msg->flags & I2C_M_STOP);
420418

421-
ret = uniphier_fi2c_master_xfer_one(adap, msg, repeat, stop);
419+
ret = uniphier_fi2c_xfer_one(adap, msg, repeat, stop);
422420
if (ret)
423421
return ret;
424422

@@ -434,7 +432,7 @@ static u32 uniphier_fi2c_functionality(struct i2c_adapter *adap)
434432
}
435433

436434
static const struct i2c_algorithm uniphier_fi2c_algo = {
437-
.master_xfer = uniphier_fi2c_master_xfer,
435+
.xfer = uniphier_fi2c_xfer,
438436
.functionality = uniphier_fi2c_functionality,
439437
};
440438

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