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arch/arm64/boot/dts/rockchip Expand file tree Collapse file tree 3 files changed +11
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lines changed Original file line number Diff line number Diff line change 291
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};
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power-domain@PX30_PD_MMC_NAND {
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reg = <PX30_PD_MMC_NAND>;
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- clocks = <&cru HCLK_NANDC>,
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- <&cru HCLK_EMMC>,
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- <&cru HCLK_SDIO>,
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- <&cru HCLK_SFC>,
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- <&cru SCLK_EMMC>,
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- <&cru SCLK_NANDC>,
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- <&cru SCLK_SDIO>,
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- <&cru SCLK_SFC>;
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+ clocks = <&cru HCLK_NANDC>,
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+ <&cru HCLK_EMMC>,
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+ <&cru HCLK_SDIO>,
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+ <&cru HCLK_SFC>,
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+ <&cru SCLK_EMMC>,
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+ <&cru SCLK_NANDC>,
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+ <&cru SCLK_SDIO>,
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+ <&cru SCLK_SFC>;
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pm_qos = <&qos_emmc>, <&qos_nand>,
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<&qos_sdio>, <&qos_sfc>;
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#power-domain-cells = <0>;
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&gmac1 {
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assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
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- assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
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+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
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phy-mode = "rgmii";
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clock_in_out = "input";
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pinctrl-names = "default";
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&mdio1 {
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rgmii_phy1: ethernet-phy@0 {
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- compatible= "ethernet-phy-ieee802.3-c22";
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- reg= <0x0>;
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ reg = <0x0>;
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};
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};
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