Skip to content

Commit f9d323e

Browse files
Zebra345superna9999
authored andcommitted
perf/amlogic: adjust register offsets
Commit "perf/amlogic: resolve conflict between canvas & pmu" changed the base address. Fixes: 2016e21 ("perf/amlogic: Add support for Amlogic meson G12 SoC DDR PMU driver") Signed-off-by: Marc Gonzalez <[email protected]> Acked-by: Will Deacon <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Neil Armstrong <[email protected]>
1 parent 33acea2 commit f9d323e

File tree

1 file changed

+17
-17
lines changed

1 file changed

+17
-17
lines changed

drivers/perf/amlogic/meson_g12_ddr_pmu.c

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -21,23 +21,23 @@
2121
#define DMC_QOS_IRQ BIT(30)
2222

2323
/* DMC bandwidth monitor register address offset */
24-
#define DMC_MON_G12_CTRL0 (0x20 << 2)
25-
#define DMC_MON_G12_CTRL1 (0x21 << 2)
26-
#define DMC_MON_G12_CTRL2 (0x22 << 2)
27-
#define DMC_MON_G12_CTRL3 (0x23 << 2)
28-
#define DMC_MON_G12_CTRL4 (0x24 << 2)
29-
#define DMC_MON_G12_CTRL5 (0x25 << 2)
30-
#define DMC_MON_G12_CTRL6 (0x26 << 2)
31-
#define DMC_MON_G12_CTRL7 (0x27 << 2)
32-
#define DMC_MON_G12_CTRL8 (0x28 << 2)
33-
34-
#define DMC_MON_G12_ALL_REQ_CNT (0x29 << 2)
35-
#define DMC_MON_G12_ALL_GRANT_CNT (0x2a << 2)
36-
#define DMC_MON_G12_ONE_GRANT_CNT (0x2b << 2)
37-
#define DMC_MON_G12_SEC_GRANT_CNT (0x2c << 2)
38-
#define DMC_MON_G12_THD_GRANT_CNT (0x2d << 2)
39-
#define DMC_MON_G12_FOR_GRANT_CNT (0x2e << 2)
40-
#define DMC_MON_G12_TIMER (0x2f << 2)
24+
#define DMC_MON_G12_CTRL0 (0x0 << 2)
25+
#define DMC_MON_G12_CTRL1 (0x1 << 2)
26+
#define DMC_MON_G12_CTRL2 (0x2 << 2)
27+
#define DMC_MON_G12_CTRL3 (0x3 << 2)
28+
#define DMC_MON_G12_CTRL4 (0x4 << 2)
29+
#define DMC_MON_G12_CTRL5 (0x5 << 2)
30+
#define DMC_MON_G12_CTRL6 (0x6 << 2)
31+
#define DMC_MON_G12_CTRL7 (0x7 << 2)
32+
#define DMC_MON_G12_CTRL8 (0x8 << 2)
33+
34+
#define DMC_MON_G12_ALL_REQ_CNT (0x9 << 2)
35+
#define DMC_MON_G12_ALL_GRANT_CNT (0xa << 2)
36+
#define DMC_MON_G12_ONE_GRANT_CNT (0xb << 2)
37+
#define DMC_MON_G12_SEC_GRANT_CNT (0xc << 2)
38+
#define DMC_MON_G12_THD_GRANT_CNT (0xd << 2)
39+
#define DMC_MON_G12_FOR_GRANT_CNT (0xe << 2)
40+
#define DMC_MON_G12_TIMER (0xf << 2)
4141

4242
/* Each bit represent a axi line */
4343
PMU_FORMAT_ATTR(event, "config:0-7");

0 commit comments

Comments
 (0)