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21 | 21 | #define DMC_QOS_IRQ BIT(30)
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22 | 22 |
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23 | 23 | /* DMC bandwidth monitor register address offset */
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24 |
| -#define DMC_MON_G12_CTRL0 (0x20 << 2) |
25 |
| -#define DMC_MON_G12_CTRL1 (0x21 << 2) |
26 |
| -#define DMC_MON_G12_CTRL2 (0x22 << 2) |
27 |
| -#define DMC_MON_G12_CTRL3 (0x23 << 2) |
28 |
| -#define DMC_MON_G12_CTRL4 (0x24 << 2) |
29 |
| -#define DMC_MON_G12_CTRL5 (0x25 << 2) |
30 |
| -#define DMC_MON_G12_CTRL6 (0x26 << 2) |
31 |
| -#define DMC_MON_G12_CTRL7 (0x27 << 2) |
32 |
| -#define DMC_MON_G12_CTRL8 (0x28 << 2) |
33 |
| - |
34 |
| -#define DMC_MON_G12_ALL_REQ_CNT (0x29 << 2) |
35 |
| -#define DMC_MON_G12_ALL_GRANT_CNT (0x2a << 2) |
36 |
| -#define DMC_MON_G12_ONE_GRANT_CNT (0x2b << 2) |
37 |
| -#define DMC_MON_G12_SEC_GRANT_CNT (0x2c << 2) |
38 |
| -#define DMC_MON_G12_THD_GRANT_CNT (0x2d << 2) |
39 |
| -#define DMC_MON_G12_FOR_GRANT_CNT (0x2e << 2) |
40 |
| -#define DMC_MON_G12_TIMER (0x2f << 2) |
| 24 | +#define DMC_MON_G12_CTRL0 (0x0 << 2) |
| 25 | +#define DMC_MON_G12_CTRL1 (0x1 << 2) |
| 26 | +#define DMC_MON_G12_CTRL2 (0x2 << 2) |
| 27 | +#define DMC_MON_G12_CTRL3 (0x3 << 2) |
| 28 | +#define DMC_MON_G12_CTRL4 (0x4 << 2) |
| 29 | +#define DMC_MON_G12_CTRL5 (0x5 << 2) |
| 30 | +#define DMC_MON_G12_CTRL6 (0x6 << 2) |
| 31 | +#define DMC_MON_G12_CTRL7 (0x7 << 2) |
| 32 | +#define DMC_MON_G12_CTRL8 (0x8 << 2) |
| 33 | + |
| 34 | +#define DMC_MON_G12_ALL_REQ_CNT (0x9 << 2) |
| 35 | +#define DMC_MON_G12_ALL_GRANT_CNT (0xa << 2) |
| 36 | +#define DMC_MON_G12_ONE_GRANT_CNT (0xb << 2) |
| 37 | +#define DMC_MON_G12_SEC_GRANT_CNT (0xc << 2) |
| 38 | +#define DMC_MON_G12_THD_GRANT_CNT (0xd << 2) |
| 39 | +#define DMC_MON_G12_FOR_GRANT_CNT (0xe << 2) |
| 40 | +#define DMC_MON_G12_TIMER (0xf << 2) |
41 | 41 |
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42 | 42 | /* Each bit represent a axi line */
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43 | 43 | PMU_FORMAT_ATTR(event, "config:0-7");
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