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nfrapradodlezcano
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thermal/drivers/mediatek/lvts: Disable low offset IRQ for minimum threshold
In order to get working interrupts, a low offset value needs to be configured. The minimum value for it is 20 Celsius, which is what is configured when there's no lower thermal trip (ie the thermal core passes -INT_MAX as low trip temperature). However, when the temperature gets that low and fluctuates around that value it causes an interrupt storm. Prevent that interrupt storm by not enabling the low offset interrupt if the low threshold is the minimum one. Cc: [email protected] Fixes: 77354ea ("thermal/drivers/mediatek/lvts_thermal: Don't leave threshold zeroed") Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Signed-off-by: Nícolas F. R. A. Prado <[email protected]> Link: https://lore.kernel.org/r/20250113-mt8192-lvts-filtered-suspend-fix-v2-3-07a25200c7c6@collabora.com Signed-off-by: Daniel Lezcano <[email protected]>
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drivers/thermal/mediatek/lvts_thermal.c

Lines changed: 35 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -67,10 +67,14 @@
6767
#define LVTS_CALSCALE_CONF 0x300
6868
#define LVTS_MONINT_CONF 0x0300318C
6969

70-
#define LVTS_MONINT_OFFSET_SENSOR0 0xC
71-
#define LVTS_MONINT_OFFSET_SENSOR1 0x180
72-
#define LVTS_MONINT_OFFSET_SENSOR2 0x3000
73-
#define LVTS_MONINT_OFFSET_SENSOR3 0x3000000
70+
#define LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR0 BIT(3)
71+
#define LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR1 BIT(8)
72+
#define LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR2 BIT(13)
73+
#define LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR3 BIT(25)
74+
#define LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR0 BIT(2)
75+
#define LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR1 BIT(7)
76+
#define LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR2 BIT(12)
77+
#define LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR3 BIT(24)
7478

7579
#define LVTS_INT_SENSOR0 0x0009001F
7680
#define LVTS_INT_SENSOR1 0x001203E0
@@ -326,11 +330,17 @@ static int lvts_get_temp(struct thermal_zone_device *tz, int *temp)
326330

327331
static void lvts_update_irq_mask(struct lvts_ctrl *lvts_ctrl)
328332
{
329-
static const u32 masks[] = {
330-
LVTS_MONINT_OFFSET_SENSOR0,
331-
LVTS_MONINT_OFFSET_SENSOR1,
332-
LVTS_MONINT_OFFSET_SENSOR2,
333-
LVTS_MONINT_OFFSET_SENSOR3,
333+
static const u32 high_offset_inten_masks[] = {
334+
LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR0,
335+
LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR1,
336+
LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR2,
337+
LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR3,
338+
};
339+
static const u32 low_offset_inten_masks[] = {
340+
LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR0,
341+
LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR1,
342+
LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR2,
343+
LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR3,
334344
};
335345
u32 value = 0;
336346
int i;
@@ -339,10 +349,22 @@ static void lvts_update_irq_mask(struct lvts_ctrl *lvts_ctrl)
339349

340350
for (i = 0; i < ARRAY_SIZE(masks); i++) {
341351
if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh
342-
&& lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh)
343-
value |= masks[i];
344-
else
345-
value &= ~masks[i];
352+
&& lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh) {
353+
/*
354+
* The minimum threshold needs to be configured in the
355+
* OFFSETL register to get working interrupts, but we
356+
* don't actually want to generate interrupts when
357+
* crossing it.
358+
*/
359+
if (lvts_ctrl->low_thresh == -INT_MAX) {
360+
value &= ~low_offset_inten_masks[i];
361+
value |= high_offset_inten_masks[i];
362+
} else {
363+
value |= low_offset_inten_masks[i] | high_offset_inten_masks[i];
364+
}
365+
} else {
366+
value &= ~(low_offset_inten_masks[i] | high_offset_inten_masks[i]);
367+
}
346368
}
347369

348370
writel(value, LVTS_MONINT(lvts_ctrl->base));

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