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Merge branch 'remotes/lorenzo/pci/tegra'
- Revert tegra RAW fixup that caused a regression (Nicolas Chauvet) - Remove PLL power supplies from tegra driver and DT binding (Thierry Reding) * remotes/lorenzo/pci/tegra: PCI: tegra: Remove PLL power supplies dt-bindings: pci: tegra: Remove PLL power supplies PCI: tegra: Revert tegra124 raw_violation_fixup
2 parents 21c04e0 + a6fbb4a commit fa6cc79

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Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt

Lines changed: 0 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -112,28 +112,16 @@ Power supplies for Tegra124:
112112
- Required:
113113
- avddio-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
114114
- dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
115-
- avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
116-
supply 1.05 V.
117115
- hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
118116
Must supply 3.3 V.
119-
- hvdd-pex-pll-e-supply: High-voltage supply for PLLE (shared with USB3).
120-
Must supply 3.3 V.
121117
- vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
122118
supply 2.8-3.3 V.
123-
- avdd-pll-erefe-supply: Power supply for PLLE (shared with USB3). Must
124-
supply 1.05 V.
125119

126120
Power supplies for Tegra210:
127121
- Required:
128-
- avdd-pll-uerefe-supply: Power supply for PLLE (shared with USB3). Must
129-
supply 1.05 V.
130122
- hvddio-pex-supply: High-voltage supply for PCIe I/O and PCIe output
131123
clocks. Must supply 1.8 V.
132124
- dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
133-
- dvdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
134-
supply 1.05 V.
135-
- hvdd-pex-pll-e-supply: High-voltage supply for PLLE (shared with USB3).
136-
Must supply 3.3 V.
137125
- vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
138126
supply 1.8 V.
139127

drivers/pci/controller/pci-tegra.c

Lines changed: 2 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -181,13 +181,6 @@
181181

182182
#define AFI_PEXBIAS_CTRL_0 0x168
183183

184-
#define RP_PRIV_XP_DL 0x00000494
185-
#define RP_PRIV_XP_DL_GEN2_UPD_FC_TSHOLD (0x1ff << 1)
186-
187-
#define RP_RX_HDR_LIMIT 0x00000e00
188-
#define RP_RX_HDR_LIMIT_PW_MASK (0xff << 8)
189-
#define RP_RX_HDR_LIMIT_PW (0x0e << 8)
190-
191184
#define RP_ECTL_2_R1 0x00000e84
192185
#define RP_ECTL_2_R1_RX_CTLE_1C_MASK 0xffff
193186

@@ -323,7 +316,6 @@ struct tegra_pcie_soc {
323316
bool program_uphy;
324317
bool update_clamp_threshold;
325318
bool program_deskew_time;
326-
bool raw_violation_fixup;
327319
bool update_fc_timer;
328320
bool has_cache_bars;
329321
struct {
@@ -659,23 +651,6 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port)
659651
writel(value, port->base + RP_VEND_CTL0);
660652
}
661653

662-
/* Fixup for read after write violation. */
663-
if (soc->raw_violation_fixup) {
664-
value = readl(port->base + RP_RX_HDR_LIMIT);
665-
value &= ~RP_RX_HDR_LIMIT_PW_MASK;
666-
value |= RP_RX_HDR_LIMIT_PW;
667-
writel(value, port->base + RP_RX_HDR_LIMIT);
668-
669-
value = readl(port->base + RP_PRIV_XP_DL);
670-
value |= RP_PRIV_XP_DL_GEN2_UPD_FC_TSHOLD;
671-
writel(value, port->base + RP_PRIV_XP_DL);
672-
673-
value = readl(port->base + RP_VEND_XP);
674-
value &= ~RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK;
675-
value |= soc->update_fc_threshold;
676-
writel(value, port->base + RP_VEND_XP);
677-
}
678-
679654
if (soc->update_fc_timer) {
680655
value = readl(port->base + RP_VEND_XP);
681656
value &= ~RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK;
@@ -2025,22 +2000,19 @@ static int tegra_pcie_get_regulators(struct tegra_pcie *pcie, u32 lane_mask)
20252000
pcie->supplies[i++].supply = "hvdd-pex";
20262001
pcie->supplies[i++].supply = "vddio-pexctl-aud";
20272002
} else if (of_device_is_compatible(np, "nvidia,tegra210-pcie")) {
2028-
pcie->num_supplies = 6;
2003+
pcie->num_supplies = 3;
20292004

20302005
pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies,
20312006
sizeof(*pcie->supplies),
20322007
GFP_KERNEL);
20332008
if (!pcie->supplies)
20342009
return -ENOMEM;
20352010

2036-
pcie->supplies[i++].supply = "avdd-pll-uerefe";
20372011
pcie->supplies[i++].supply = "hvddio-pex";
20382012
pcie->supplies[i++].supply = "dvddio-pex";
2039-
pcie->supplies[i++].supply = "dvdd-pex-pll";
2040-
pcie->supplies[i++].supply = "hvdd-pex-pll-e";
20412013
pcie->supplies[i++].supply = "vddio-pex-ctl";
20422014
} else if (of_device_is_compatible(np, "nvidia,tegra124-pcie")) {
2043-
pcie->num_supplies = 7;
2015+
pcie->num_supplies = 4;
20442016

20452017
pcie->supplies = devm_kcalloc(dev, pcie->num_supplies,
20462018
sizeof(*pcie->supplies),
@@ -2050,11 +2022,8 @@ static int tegra_pcie_get_regulators(struct tegra_pcie *pcie, u32 lane_mask)
20502022

20512023
pcie->supplies[i++].supply = "avddio-pex";
20522024
pcie->supplies[i++].supply = "dvddio-pex";
2053-
pcie->supplies[i++].supply = "avdd-pex-pll";
20542025
pcie->supplies[i++].supply = "hvdd-pex";
2055-
pcie->supplies[i++].supply = "hvdd-pex-pll-e";
20562026
pcie->supplies[i++].supply = "vddio-pex-ctl";
2057-
pcie->supplies[i++].supply = "avdd-pll-erefe";
20582027
} else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) {
20592028
bool need_pexa = false, need_pexb = false;
20602029

@@ -2416,7 +2385,6 @@ static const struct tegra_pcie_soc tegra20_pcie = {
24162385
.program_uphy = true,
24172386
.update_clamp_threshold = false,
24182387
.program_deskew_time = false,
2419-
.raw_violation_fixup = false,
24202388
.update_fc_timer = false,
24212389
.has_cache_bars = true,
24222390
.ectl.enable = false,
@@ -2446,7 +2414,6 @@ static const struct tegra_pcie_soc tegra30_pcie = {
24462414
.program_uphy = true,
24472415
.update_clamp_threshold = false,
24482416
.program_deskew_time = false,
2449-
.raw_violation_fixup = false,
24502417
.update_fc_timer = false,
24512418
.has_cache_bars = false,
24522419
.ectl.enable = false,
@@ -2459,8 +2426,6 @@ static const struct tegra_pcie_soc tegra124_pcie = {
24592426
.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
24602427
.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
24612428
.pads_refclk_cfg0 = 0x44ac44ac,
2462-
/* FC threshold is bit[25:18] */
2463-
.update_fc_threshold = 0x03fc0000,
24642429
.has_pex_clkreq_en = true,
24652430
.has_pex_bias_ctrl = true,
24662431
.has_intr_prsnt_sense = true,
@@ -2470,7 +2435,6 @@ static const struct tegra_pcie_soc tegra124_pcie = {
24702435
.program_uphy = true,
24712436
.update_clamp_threshold = true,
24722437
.program_deskew_time = false,
2473-
.raw_violation_fixup = true,
24742438
.update_fc_timer = false,
24752439
.has_cache_bars = false,
24762440
.ectl.enable = false,
@@ -2494,7 +2458,6 @@ static const struct tegra_pcie_soc tegra210_pcie = {
24942458
.program_uphy = true,
24952459
.update_clamp_threshold = true,
24962460
.program_deskew_time = true,
2497-
.raw_violation_fixup = false,
24982461
.update_fc_timer = true,
24992462
.has_cache_bars = false,
25002463
.ectl = {
@@ -2536,7 +2499,6 @@ static const struct tegra_pcie_soc tegra186_pcie = {
25362499
.program_uphy = false,
25372500
.update_clamp_threshold = false,
25382501
.program_deskew_time = false,
2539-
.raw_violation_fixup = false,
25402502
.update_fc_timer = false,
25412503
.has_cache_bars = false,
25422504
.ectl.enable = false,

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