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bebarinobebarino
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Merge branch 'clk-renesas' into clk-next
* clk-renesas: clk: renesas: cpg-mssr: Add r8a774e1 support dt-bindings: clock: renesas,cpg-mssr: Document r8a774e1 clk: renesas: Add r8a774e1 CPG Core Clock Definitions dt-bindings: power: Add r8a774e1 SYSC power domain definitions
2 parents 73d6bd7 + 210f724 commit fca1484

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8 files changed

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‎Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml

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@@ -33,6 +33,7 @@ properties:
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- renesas,r8a774a1-cpg-mssr # RZ/G2M
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- renesas,r8a774b1-cpg-mssr # RZ/G2N
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- renesas,r8a774c0-cpg-mssr # RZ/G2E
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- renesas,r8a774e1-cpg-mssr # RZ/G2H
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- renesas,r8a7790-cpg-mssr # R-Car H2
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- renesas,r8a7791-cpg-mssr # R-Car M2-W
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- renesas,r8a7792-cpg-mssr # R-Car V2H

‎drivers/clk/renesas/Kconfig

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Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@ config CLK_RENESAS
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select CLK_R8A774A1 if ARCH_R8A774A1
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select CLK_R8A774B1 if ARCH_R8A774B1
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select CLK_R8A774C0 if ARCH_R8A774C0
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select CLK_R8A774E1 if ARCH_R8A774E1
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select CLK_R8A7778 if ARCH_R8A7778
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select CLK_R8A7779 if ARCH_R8A7779
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select CLK_R8A7790 if ARCH_R8A7790
@@ -84,6 +85,10 @@ config CLK_R8A774C0
8485
bool "RZ/G2E clock support" if COMPILE_TEST
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select CLK_RCAR_GEN3_CPG
8687

88+
config CLK_R8A774E1
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bool "RZ/G2H clock support" if COMPILE_TEST
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select CLK_RCAR_GEN3_CPG
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8792
config CLK_R8A7778
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bool "R-Car M1A clock support" if COMPILE_TEST
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select CLK_RENESAS_CPG_MSTP

‎drivers/clk/renesas/Makefile

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Original file line numberDiff line numberDiff line change
@@ -12,6 +12,7 @@ obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o
1313
obj-$(CONFIG_CLK_R8A774B1) += r8a774b1-cpg-mssr.o
1414
obj-$(CONFIG_CLK_R8A774C0) += r8a774c0-cpg-mssr.o
15+
obj-$(CONFIG_CLK_R8A774E1) += r8a774e1-cpg-mssr.o
1516
obj-$(CONFIG_CLK_R8A7778) += clk-r8a7778.o
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obj-$(CONFIG_CLK_R8A7779) += clk-r8a7779.o
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obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o

‎drivers/clk/renesas/r8a774e1-cpg-mssr.c

Lines changed: 349 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,349 @@
1+
// SPDX-License-Identifier: GPL-2.0
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/*
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* r8a774e1 Clock Pulse Generator / Module Standby and Software Reset
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*
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* Copyright (C) 2020 Renesas Electronics Corp.
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*
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* Based on r8a7795-cpg-mssr.c
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*
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* Copyright (C) 2015 Glider bvba
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*/
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#include <linux/device.h>
13+
#include <linux/init.h>
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#include <linux/kernel.h>
15+
#include <linux/soc/renesas/rcar-rst.h>
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#include <dt-bindings/clock/r8a774e1-cpg-mssr.h>
18+
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#include "renesas-cpg-mssr.h"
20+
#include "rcar-gen3-cpg.h"
21+
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enum clk_ids {
23+
/* Core Clock Outputs exported to DT */
24+
LAST_DT_CORE_CLK = R8A774E1_CLK_CANFD,
25+
26+
/* External Input Clocks */
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CLK_EXTAL,
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CLK_EXTALR,
29+
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/* Internal Core Clocks */
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CLK_MAIN,
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CLK_PLL0,
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CLK_PLL1,
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CLK_PLL2,
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CLK_PLL3,
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CLK_PLL4,
37+
CLK_PLL1_DIV2,
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CLK_PLL1_DIV4,
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CLK_S0,
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CLK_S1,
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CLK_S2,
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CLK_S3,
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CLK_SDSRC,
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CLK_RPCSRC,
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CLK_RINT,
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/* Module Clocks */
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MOD_CLK_BASE
49+
};
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static const struct cpg_core_clk r8a774e1_core_clks[] __initconst = {
52+
/* External Clock Inputs */
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DEF_INPUT("extal", CLK_EXTAL),
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DEF_INPUT("extalr", CLK_EXTALR),
55+
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/* Internal Core Clocks */
57+
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
58+
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
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DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
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DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
61+
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
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DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
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DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
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DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
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DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
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DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
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DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
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DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
70+
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
71+
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
72+
73+
DEF_BASE("rpc", R8A774E1_CLK_RPC, CLK_TYPE_GEN3_RPC,
74+
CLK_RPCSRC),
75+
DEF_BASE("rpcd2", R8A774E1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
76+
R8A774E1_CLK_RPC),
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DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
79+
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/* Core Clock Outputs */
81+
DEF_GEN3_Z("z", R8A774E1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
82+
DEF_GEN3_Z("z2", R8A774E1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
83+
DEF_FIXED("ztr", R8A774E1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
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DEF_FIXED("ztrd2", R8A774E1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
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DEF_FIXED("zt", R8A774E1_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
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DEF_FIXED("zx", R8A774E1_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
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DEF_FIXED("s0d1", R8A774E1_CLK_S0D1, CLK_S0, 1, 1),
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DEF_FIXED("s0d2", R8A774E1_CLK_S0D2, CLK_S0, 2, 1),
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DEF_FIXED("s0d3", R8A774E1_CLK_S0D3, CLK_S0, 3, 1),
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DEF_FIXED("s0d4", R8A774E1_CLK_S0D4, CLK_S0, 4, 1),
91+
DEF_FIXED("s0d6", R8A774E1_CLK_S0D6, CLK_S0, 6, 1),
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DEF_FIXED("s0d8", R8A774E1_CLK_S0D8, CLK_S0, 8, 1),
93+
DEF_FIXED("s0d12", R8A774E1_CLK_S0D12, CLK_S0, 12, 1),
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DEF_FIXED("s1d2", R8A774E1_CLK_S1D2, CLK_S1, 2, 1),
95+
DEF_FIXED("s1d4", R8A774E1_CLK_S1D4, CLK_S1, 4, 1),
96+
DEF_FIXED("s2d1", R8A774E1_CLK_S2D1, CLK_S2, 1, 1),
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DEF_FIXED("s2d2", R8A774E1_CLK_S2D2, CLK_S2, 2, 1),
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DEF_FIXED("s2d4", R8A774E1_CLK_S2D4, CLK_S2, 4, 1),
99+
DEF_FIXED("s3d1", R8A774E1_CLK_S3D1, CLK_S3, 1, 1),
100+
DEF_FIXED("s3d2", R8A774E1_CLK_S3D2, CLK_S3, 2, 1),
101+
DEF_FIXED("s3d4", R8A774E1_CLK_S3D4, CLK_S3, 4, 1),
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103+
DEF_GEN3_SD("sd0", R8A774E1_CLK_SD0, CLK_SDSRC, 0x074),
104+
DEF_GEN3_SD("sd1", R8A774E1_CLK_SD1, CLK_SDSRC, 0x078),
105+
DEF_GEN3_SD("sd2", R8A774E1_CLK_SD2, CLK_SDSRC, 0x268),
106+
DEF_GEN3_SD("sd3", R8A774E1_CLK_SD3, CLK_SDSRC, 0x26c),
107+
108+
DEF_FIXED("cl", R8A774E1_CLK_CL, CLK_PLL1_DIV2, 48, 1),
109+
DEF_FIXED("cr", R8A774E1_CLK_CR, CLK_PLL1_DIV4, 2, 1),
110+
DEF_FIXED("cp", R8A774E1_CLK_CP, CLK_EXTAL, 2, 1),
111+
DEF_FIXED("cpex", R8A774E1_CLK_CPEX, CLK_EXTAL, 2, 1),
112+
113+
DEF_DIV6P1("canfd", R8A774E1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
114+
DEF_DIV6P1("csi0", R8A774E1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
115+
DEF_DIV6P1("mso", R8A774E1_CLK_MSO, CLK_PLL1_DIV4, 0x014),
116+
DEF_DIV6P1("hdmi", R8A774E1_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
117+
118+
DEF_GEN3_OSC("osc", R8A774E1_CLK_OSC, CLK_EXTAL, 8),
119+
120+
DEF_BASE("r", R8A774E1_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
121+
};
122+
123+
static const struct mssr_mod_clk r8a774e1_mod_clks[] __initconst = {
124+
DEF_MOD("fdp1-1", 118, R8A774E1_CLK_S0D1),
125+
DEF_MOD("fdp1-0", 119, R8A774E1_CLK_S0D1),
126+
DEF_MOD("tmu4", 121, R8A774E1_CLK_S0D6),
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DEF_MOD("tmu3", 122, R8A774E1_CLK_S3D2),
128+
DEF_MOD("tmu2", 123, R8A774E1_CLK_S3D2),
129+
DEF_MOD("tmu1", 124, R8A774E1_CLK_S3D2),
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DEF_MOD("tmu0", 125, R8A774E1_CLK_CP),
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DEF_MOD("vcplf", 130, R8A774E1_CLK_S2D1),
132+
DEF_MOD("vdpb", 131, R8A774E1_CLK_S2D1),
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DEF_MOD("scif5", 202, R8A774E1_CLK_S3D4),
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DEF_MOD("scif4", 203, R8A774E1_CLK_S3D4),
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DEF_MOD("scif3", 204, R8A774E1_CLK_S3D4),
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DEF_MOD("scif1", 206, R8A774E1_CLK_S3D4),
137+
DEF_MOD("scif0", 207, R8A774E1_CLK_S3D4),
138+
DEF_MOD("msiof3", 208, R8A774E1_CLK_MSO),
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DEF_MOD("msiof2", 209, R8A774E1_CLK_MSO),
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DEF_MOD("msiof1", 210, R8A774E1_CLK_MSO),
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DEF_MOD("msiof0", 211, R8A774E1_CLK_MSO),
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DEF_MOD("sys-dmac2", 217, R8A774E1_CLK_S3D1),
143+
DEF_MOD("sys-dmac1", 218, R8A774E1_CLK_S3D1),
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DEF_MOD("sys-dmac0", 219, R8A774E1_CLK_S0D3),
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DEF_MOD("cmt3", 300, R8A774E1_CLK_R),
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DEF_MOD("cmt2", 301, R8A774E1_CLK_R),
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DEF_MOD("cmt1", 302, R8A774E1_CLK_R),
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DEF_MOD("cmt0", 303, R8A774E1_CLK_R),
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DEF_MOD("tpu0", 304, R8A774E1_CLK_S3D4),
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DEF_MOD("scif2", 310, R8A774E1_CLK_S3D4),
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DEF_MOD("sdif3", 311, R8A774E1_CLK_SD3),
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DEF_MOD("sdif2", 312, R8A774E1_CLK_SD2),
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DEF_MOD("sdif1", 313, R8A774E1_CLK_SD1),
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DEF_MOD("sdif0", 314, R8A774E1_CLK_SD0),
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DEF_MOD("pcie1", 318, R8A774E1_CLK_S3D1),
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DEF_MOD("pcie0", 319, R8A774E1_CLK_S3D1),
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DEF_MOD("usb3-if0", 328, R8A774E1_CLK_S3D1),
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DEF_MOD("usb-dmac0", 330, R8A774E1_CLK_S3D1),
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DEF_MOD("usb-dmac1", 331, R8A774E1_CLK_S3D1),
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DEF_MOD("rwdt", 402, R8A774E1_CLK_R),
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DEF_MOD("intc-ex", 407, R8A774E1_CLK_CP),
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DEF_MOD("intc-ap", 408, R8A774E1_CLK_S0D3),
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DEF_MOD("audmac1", 501, R8A774E1_CLK_S1D2),
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DEF_MOD("audmac0", 502, R8A774E1_CLK_S1D2),
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DEF_MOD("hscif4", 516, R8A774E1_CLK_S3D1),
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DEF_MOD("hscif3", 517, R8A774E1_CLK_S3D1),
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DEF_MOD("hscif2", 518, R8A774E1_CLK_S3D1),
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DEF_MOD("hscif1", 519, R8A774E1_CLK_S3D1),
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DEF_MOD("hscif0", 520, R8A774E1_CLK_S3D1),
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DEF_MOD("thermal", 522, R8A774E1_CLK_CP),
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DEF_MOD("pwm", 523, R8A774E1_CLK_S0D12),
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DEF_MOD("fcpvd1", 602, R8A774E1_CLK_S0D2),
173+
DEF_MOD("fcpvd0", 603, R8A774E1_CLK_S0D2),
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DEF_MOD("fcpvb1", 606, R8A774E1_CLK_S0D1),
175+
DEF_MOD("fcpvb0", 607, R8A774E1_CLK_S0D1),
176+
DEF_MOD("fcpvi1", 610, R8A774E1_CLK_S0D1),
177+
DEF_MOD("fcpvi0", 611, R8A774E1_CLK_S0D1),
178+
DEF_MOD("fcpf1", 614, R8A774E1_CLK_S0D1),
179+
DEF_MOD("fcpf0", 615, R8A774E1_CLK_S0D1),
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DEF_MOD("fcpcs", 619, R8A774E1_CLK_S0D1),
181+
DEF_MOD("vspd1", 622, R8A774E1_CLK_S0D2),
182+
DEF_MOD("vspd0", 623, R8A774E1_CLK_S0D2),
183+
DEF_MOD("vspbc", 624, R8A774E1_CLK_S0D1),
184+
DEF_MOD("vspbd", 626, R8A774E1_CLK_S0D1),
185+
DEF_MOD("vspi1", 630, R8A774E1_CLK_S0D1),
186+
DEF_MOD("vspi0", 631, R8A774E1_CLK_S0D1),
187+
DEF_MOD("ehci1", 702, R8A774E1_CLK_S3D2),
188+
DEF_MOD("ehci0", 703, R8A774E1_CLK_S3D2),
189+
DEF_MOD("hsusb", 704, R8A774E1_CLK_S3D2),
190+
DEF_MOD("csi20", 714, R8A774E1_CLK_CSI0),
191+
DEF_MOD("csi40", 716, R8A774E1_CLK_CSI0),
192+
DEF_MOD("du3", 721, R8A774E1_CLK_S2D1),
193+
DEF_MOD("du1", 723, R8A774E1_CLK_S2D1),
194+
DEF_MOD("du0", 724, R8A774E1_CLK_S2D1),
195+
DEF_MOD("lvds", 727, R8A774E1_CLK_S0D4),
196+
DEF_MOD("hdmi0", 729, R8A774E1_CLK_HDMI),
197+
DEF_MOD("vin7", 804, R8A774E1_CLK_S0D2),
198+
DEF_MOD("vin6", 805, R8A774E1_CLK_S0D2),
199+
DEF_MOD("vin5", 806, R8A774E1_CLK_S0D2),
200+
DEF_MOD("vin4", 807, R8A774E1_CLK_S0D2),
201+
DEF_MOD("vin3", 808, R8A774E1_CLK_S0D2),
202+
DEF_MOD("vin2", 809, R8A774E1_CLK_S0D2),
203+
DEF_MOD("vin1", 810, R8A774E1_CLK_S0D2),
204+
DEF_MOD("vin0", 811, R8A774E1_CLK_S0D2),
205+
DEF_MOD("etheravb", 812, R8A774E1_CLK_S0D6),
206+
DEF_MOD("sata0", 815, R8A774E1_CLK_S3D2),
207+
DEF_MOD("gpio7", 905, R8A774E1_CLK_S3D4),
208+
DEF_MOD("gpio6", 906, R8A774E1_CLK_S3D4),
209+
DEF_MOD("gpio5", 907, R8A774E1_CLK_S3D4),
210+
DEF_MOD("gpio4", 908, R8A774E1_CLK_S3D4),
211+
DEF_MOD("gpio3", 909, R8A774E1_CLK_S3D4),
212+
DEF_MOD("gpio2", 910, R8A774E1_CLK_S3D4),
213+
DEF_MOD("gpio1", 911, R8A774E1_CLK_S3D4),
214+
DEF_MOD("gpio0", 912, R8A774E1_CLK_S3D4),
215+
DEF_MOD("can-fd", 914, R8A774E1_CLK_S3D2),
216+
DEF_MOD("can-if1", 915, R8A774E1_CLK_S3D4),
217+
DEF_MOD("can-if0", 916, R8A774E1_CLK_S3D4),
218+
DEF_MOD("rpc-if", 917, R8A774E1_CLK_RPCD2),
219+
DEF_MOD("i2c6", 918, R8A774E1_CLK_S0D6),
220+
DEF_MOD("i2c5", 919, R8A774E1_CLK_S0D6),
221+
DEF_MOD("adg", 922, R8A774E1_CLK_S0D1),
222+
DEF_MOD("i2c-dvfs", 926, R8A774E1_CLK_CP),
223+
DEF_MOD("i2c4", 927, R8A774E1_CLK_S0D6),
224+
DEF_MOD("i2c3", 928, R8A774E1_CLK_S0D6),
225+
DEF_MOD("i2c2", 929, R8A774E1_CLK_S3D2),
226+
DEF_MOD("i2c1", 930, R8A774E1_CLK_S3D2),
227+
DEF_MOD("i2c0", 931, R8A774E1_CLK_S3D2),
228+
DEF_MOD("ssi-all", 1005, R8A774E1_CLK_S3D4),
229+
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
230+
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
231+
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
232+
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
233+
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
234+
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
235+
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
236+
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
237+
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
238+
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
239+
DEF_MOD("scu-all", 1017, R8A774E1_CLK_S3D4),
240+
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
241+
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
242+
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
243+
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
244+
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
245+
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
246+
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
247+
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
248+
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
249+
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
250+
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
251+
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
252+
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
253+
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
254+
};
255+
256+
static const unsigned int r8a774e1_crit_mod_clks[] __initconst = {
257+
MOD_CLK_ID(402), /* RWDT */
258+
MOD_CLK_ID(408), /* INTC-AP (GIC) */
259+
};
260+
261+
/*
262+
* CPG Clock Data
263+
*/
264+
265+
/*
266+
* MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
267+
* 14 13 19 17 (MHz)
268+
*-------------------------------------------------------------------------
269+
* 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16
270+
* 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16
271+
* 0 0 1 0 Prohibited setting
272+
* 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16
273+
* 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19
274+
* 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19
275+
* 0 1 1 0 Prohibited setting
276+
* 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19
277+
* 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24
278+
* 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24
279+
* 1 0 1 0 Prohibited setting
280+
* 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24
281+
* 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32
282+
* 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32
283+
* 1 1 1 0 Prohibited setting
284+
* 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32
285+
*/
286+
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
287+
(((md) & BIT(13)) >> 11) | \
288+
(((md) & BIT(19)) >> 18) | \
289+
(((md) & BIT(17)) >> 17))
290+
291+
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
292+
/* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
293+
{ 1, 192, 1, 192, 1, 16, },
294+
{ 1, 192, 1, 128, 1, 16, },
295+
{ 0, /* Prohibited setting */ },
296+
{ 1, 192, 1, 192, 1, 16, },
297+
{ 1, 160, 1, 160, 1, 19, },
298+
{ 1, 160, 1, 106, 1, 19, },
299+
{ 0, /* Prohibited setting */ },
300+
{ 1, 160, 1, 160, 1, 19, },
301+
{ 1, 128, 1, 128, 1, 24, },
302+
{ 1, 128, 1, 84, 1, 24, },
303+
{ 0, /* Prohibited setting */ },
304+
{ 1, 128, 1, 128, 1, 24, },
305+
{ 2, 192, 1, 192, 1, 32, },
306+
{ 2, 192, 1, 128, 1, 32, },
307+
{ 0, /* Prohibited setting */ },
308+
{ 2, 192, 1, 192, 1, 32, },
309+
};
310+
311+
static int __init r8a774e1_cpg_mssr_init(struct device *dev)
312+
{
313+
const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
314+
u32 cpg_mode;
315+
int error;
316+
317+
error = rcar_rst_read_mode_pins(&cpg_mode);
318+
if (error)
319+
return error;
320+
321+
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
322+
if (!cpg_pll_config->extal_div) {
323+
dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
324+
return -EINVAL;
325+
}
326+
327+
return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
328+
}
329+
330+
const struct cpg_mssr_info r8a774e1_cpg_mssr_info __initconst = {
331+
/* Core Clocks */
332+
.core_clks = r8a774e1_core_clks,
333+
.num_core_clks = ARRAY_SIZE(r8a774e1_core_clks),
334+
.last_dt_core_clk = LAST_DT_CORE_CLK,
335+
.num_total_core_clks = MOD_CLK_BASE,
336+
337+
/* Module Clocks */
338+
.mod_clks = r8a774e1_mod_clks,
339+
.num_mod_clks = ARRAY_SIZE(r8a774e1_mod_clks),
340+
.num_hw_mod_clks = 12 * 32,
341+
342+
/* Critical Module Clocks */
343+
.crit_mod_clks = r8a774e1_crit_mod_clks,
344+
.num_crit_mod_clks = ARRAY_SIZE(r8a774e1_crit_mod_clks),
345+
346+
/* Callbacks */
347+
.init = r8a774e1_cpg_mssr_init,
348+
.cpg_clk_register = rcar_gen3_cpg_clk_register,
349+
};

‎drivers/clk/renesas/renesas-cpg-mssr.c

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -721,6 +721,12 @@ static const struct of_device_id cpg_mssr_match[] = {
721721
.data = &r8a774c0_cpg_mssr_info,
722722
},
723723
#endif
724+
#ifdef CONFIG_CLK_R8A774E1
725+
{
726+
.compatible = "renesas,r8a774e1-cpg-mssr",
727+
.data = &r8a774e1_cpg_mssr_info,
728+
},
729+
#endif
724730
#ifdef CONFIG_CLK_R8A7790
725731
{
726732
.compatible = "renesas,r8a7790-cpg-mssr",

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