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clk: mediatek: Add MT8188 infrastructure clock support
Add MT8188 infrastructure clock controller which provides clock gate control for basic IP like pwm, uart, spi and so on. Signed-off-by: Garmin.Chang <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
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‎drivers/clk/mediatek/Makefile

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@@ -101,7 +101,7 @@ obj-$(CONFIG_COMMON_CLK_MT8186_VDECSYS) += clk-mt8186-vdec.o
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obj-$(CONFIG_COMMON_CLK_MT8186_VENCSYS) += clk-mt8186-venc.o
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obj-$(CONFIG_COMMON_CLK_MT8186_WPESYS) += clk-mt8186-wpe.o
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obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o \
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clk-mt8188-peri_ao.o
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clk-mt8188-peri_ao.o clk-mt8188-infra_ao.o
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obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o
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obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
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obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o

‎drivers/clk/mediatek/clk-mt8188-infra_ao.c

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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Garmin Chang <[email protected]>
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*/
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#include <dt-bindings/clock/mediatek,mt8188-clk.h>
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include "clk-gate.h"
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#include "clk-mtk.h"
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static const struct mtk_gate_regs infra_ao0_cg_regs = {
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.set_ofs = 0x80,
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.clr_ofs = 0x84,
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.sta_ofs = 0x90,
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};
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static const struct mtk_gate_regs infra_ao1_cg_regs = {
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.set_ofs = 0x88,
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.clr_ofs = 0x8c,
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.sta_ofs = 0x94,
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};
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static const struct mtk_gate_regs infra_ao2_cg_regs = {
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.set_ofs = 0xa4,
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.clr_ofs = 0xa8,
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.sta_ofs = 0xac,
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};
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static const struct mtk_gate_regs infra_ao3_cg_regs = {
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.set_ofs = 0xc0,
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.clr_ofs = 0xc4,
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.sta_ofs = 0xc8,
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};
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static const struct mtk_gate_regs infra_ao4_cg_regs = {
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.set_ofs = 0xe0,
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.clr_ofs = 0xe4,
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.sta_ofs = 0xe8,
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};
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#define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag) \
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GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
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&mtk_clk_gate_ops_setclr, _flag)
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#define GATE_INFRA_AO0(_id, _name, _parent, _shift) \
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GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
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#define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag) \
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GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \
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&mtk_clk_gate_ops_setclr, _flag)
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#define GATE_INFRA_AO1(_id, _name, _parent, _shift) \
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GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
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#define GATE_INFRA_AO2(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &infra_ao2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
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#define GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, _flag) \
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GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao2_cg_regs, _shift, \
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&mtk_clk_gate_ops_setclr, _flag)
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#define GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, _flag) \
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GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao3_cg_regs, _shift, \
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&mtk_clk_gate_ops_setclr, _flag)
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#define GATE_INFRA_AO3(_id, _name, _parent, _shift) \
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GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, 0)
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#define GATE_INFRA_AO4_FLAGS(_id, _name, _parent, _shift, _flag) \
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GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao4_cg_regs, _shift, \
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&mtk_clk_gate_ops_setclr, _flag)
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#define GATE_INFRA_AO4(_id, _name, _parent, _shift) \
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GATE_INFRA_AO4_FLAGS(_id, _name, _parent, _shift, 0)
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static const struct mtk_gate infra_ao_clks[] = {
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/* INFRA_AO0 */
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GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_TMR, "infra_ao_pmic_tmr", "top_pwrap_ulposc", 0),
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GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_AP, "infra_ao_pmic_ap", "top_pwrap_ulposc", 1),
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GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_MD, "infra_ao_pmic_md", "top_pwrap_ulposc", 2),
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GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_CONN, "infra_ao_pmic_conn", "top_pwrap_ulposc", 3),
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/* infra_ao_sej is main clock is for secure engine with JTAG support */
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GATE_INFRA_AO0_FLAGS(CLK_INFRA_AO_SEJ, "infra_ao_sej", "top_axi", 5, CLK_IS_CRITICAL),
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GATE_INFRA_AO0(CLK_INFRA_AO_APXGPT, "infra_ao_apxgpt", "top_axi", 6),
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GATE_INFRA_AO0(CLK_INFRA_AO_GCE, "infra_ao_gce", "top_axi", 8),
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GATE_INFRA_AO0(CLK_INFRA_AO_GCE2, "infra_ao_gce2", "top_axi", 9),
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GATE_INFRA_AO0(CLK_INFRA_AO_THERM, "infra_ao_therm", "top_axi", 10),
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GATE_INFRA_AO0(CLK_INFRA_AO_PWM_HCLK, "infra_ao_pwm_h", "top_axi", 15),
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GATE_INFRA_AO0(CLK_INFRA_AO_PWM1, "infra_ao_pwm1", "top_pwm", 16),
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GATE_INFRA_AO0(CLK_INFRA_AO_PWM2, "infra_ao_pwm2", "top_pwm", 17),
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GATE_INFRA_AO0(CLK_INFRA_AO_PWM3, "infra_ao_pwm3", "top_pwm", 18),
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GATE_INFRA_AO0(CLK_INFRA_AO_PWM4, "infra_ao_pwm4", "top_pwm", 19),
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GATE_INFRA_AO0(CLK_INFRA_AO_PWM, "infra_ao_pwm", "top_pwm", 21),
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GATE_INFRA_AO0(CLK_INFRA_AO_UART0, "infra_ao_uart0", "top_uart", 22),
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GATE_INFRA_AO0(CLK_INFRA_AO_UART1, "infra_ao_uart1", "top_uart", 23),
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GATE_INFRA_AO0(CLK_INFRA_AO_UART2, "infra_ao_uart2", "top_uart", 24),
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GATE_INFRA_AO0(CLK_INFRA_AO_UART3, "infra_ao_uart3", "top_uart", 25),
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GATE_INFRA_AO0(CLK_INFRA_AO_UART4, "infra_ao_uart4", "top_uart", 26),
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GATE_INFRA_AO0(CLK_INFRA_AO_GCE_26M, "infra_ao_gce_26m", "clk26m", 27),
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GATE_INFRA_AO0(CLK_INFRA_AO_CQ_DMA_FPC, "infra_ao_dma", "pad_fpc_ck", 28),
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GATE_INFRA_AO0(CLK_INFRA_AO_UART5, "infra_ao_uart5", "top_uart", 29),
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/* INFRA_AO1 */
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GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_26M, "infra_ao_hdmi_26m", "clk26m", 0),
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GATE_INFRA_AO1(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "top_spi", 1),
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GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0, "infra_ao_msdc0", "top_msdc5hclk", 2),
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GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1, "infra_ao_msdc1", "top_axi", 4),
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GATE_INFRA_AO1(CLK_INFRA_AO_MSDC2, "infra_ao_msdc2", "top_axi", 5),
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GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0_SRC, "infra_ao_msdc0_clk", "top_msdc50_0", 6),
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/* infra_ao_dvfsrc is for internal DVFS usage, should not be handled by Linux. */
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GATE_INFRA_AO1_FLAGS(CLK_INFRA_AO_DVFSRC, "infra_ao_dvfsrc",
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"clk26m", 7, CLK_IS_CRITICAL),
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GATE_INFRA_AO1(CLK_INFRA_AO_TRNG, "infra_ao_trng", "top_axi", 9),
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GATE_INFRA_AO1(CLK_INFRA_AO_AUXADC, "infra_ao_auxadc", "clk26m", 10),
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GATE_INFRA_AO1(CLK_INFRA_AO_CPUM, "infra_ao_cpum", "top_axi", 11),
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GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_32K, "infra_ao_hdmi_32k", "clk32k", 12),
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GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_HCLK, "infra_ao_cec_66m_hclk", "top_axi", 13),
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GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_26M, "infra_ao_pcie_tl_26m", "clk26m", 15),
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GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1_SRC, "infra_ao_msdc1_clk", "top_msdc30_1", 16),
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GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_BCLK, "infra_ao_cec_66m_bclk", "top_axi", 17),
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GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_96M, "infra_ao_pcie_tl_96m", "top_tl", 18),
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/* infra_ao_dapc is for device access permission control module */
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GATE_INFRA_AO1_FLAGS(CLK_INFRA_AO_DEVICE_APC, "infra_ao_dapc",
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"top_axi", 20, CLK_IS_CRITICAL),
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GATE_INFRA_AO1(CLK_INFRA_AO_ECC_66M_HCLK, "infra_ao_ecc_66m_hclk", "top_axi", 23),
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GATE_INFRA_AO1(CLK_INFRA_AO_DEBUGSYS, "infra_ao_debugsys", "top_axi", 24),
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GATE_INFRA_AO1(CLK_INFRA_AO_AUDIO, "infra_ao_audio", "top_axi", 25),
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GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_32K, "infra_ao_pcie_tl_32k", "clk32k", 26),
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GATE_INFRA_AO1(CLK_INFRA_AO_DBG_TRACE, "infra_ao_dbg_trace", "top_axi", 29),
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GATE_INFRA_AO1(CLK_INFRA_AO_DRAMC_F26M, "infra_ao_dramc26", "clk26m", 31),
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/* INFRA_AO2 */
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GATE_INFRA_AO2(CLK_INFRA_AO_IRTX, "infra_ao_irtx", "top_axi", 0),
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GATE_INFRA_AO2(CLK_INFRA_AO_DISP_PWM, "infra_ao_disp_pwm", "top_disp_pwm0", 2),
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GATE_INFRA_AO2(CLK_INFRA_AO_CLDMA_BCLK, "infra_ao_cldmabclk", "top_axi", 3),
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GATE_INFRA_AO2(CLK_INFRA_AO_AUDIO_26M_BCLK, "infra_ao_audio26m", "clk26m", 4),
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GATE_INFRA_AO2(CLK_INFRA_AO_SPI1, "infra_ao_spi1", "top_spi", 6),
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GATE_INFRA_AO2(CLK_INFRA_AO_SPI2, "infra_ao_spi2", "top_spi", 9),
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GATE_INFRA_AO2(CLK_INFRA_AO_SPI3, "infra_ao_spi3", "top_spi", 10),
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GATE_INFRA_AO2_FLAGS(CLK_INFRA_AO_FSSPM, "infra_ao_fsspm",
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"top_sspm", 15, CLK_IS_CRITICAL),
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GATE_INFRA_AO2_FLAGS(CLK_INFRA_AO_SSPM_BUS_HCLK, "infra_ao_sspm_hclk",
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"top_axi", 17, CLK_IS_CRITICAL),
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GATE_INFRA_AO2(CLK_INFRA_AO_APDMA_BCLK, "infra_ao_apdma_bclk", "top_axi", 18),
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GATE_INFRA_AO2(CLK_INFRA_AO_SPI4, "infra_ao_spi4", "top_spi", 25),
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GATE_INFRA_AO2(CLK_INFRA_AO_SPI5, "infra_ao_spi5", "top_spi", 26),
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GATE_INFRA_AO2(CLK_INFRA_AO_CQ_DMA, "infra_ao_cq_dma", "top_axi", 27),
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/* INFRA_AO3 */
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GATE_INFRA_AO3(CLK_INFRA_AO_MSDC0_SELF, "infra_ao_msdc0sf", "top_msdc50_0", 0),
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GATE_INFRA_AO3(CLK_INFRA_AO_MSDC1_SELF, "infra_ao_msdc1sf", "top_msdc50_0", 1),
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GATE_INFRA_AO3(CLK_INFRA_AO_MSDC2_SELF, "infra_ao_msdc2sf", "top_msdc50_0", 2),
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GATE_INFRA_AO3(CLK_INFRA_AO_I2S_DMA, "infra_ao_i2s_dma", "top_axi", 5),
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GATE_INFRA_AO3(CLK_INFRA_AO_AP_MSDC0, "infra_ao_ap_msdc0", "top_msdc50_0", 7),
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GATE_INFRA_AO3(CLK_INFRA_AO_MD_MSDC0, "infra_ao_md_msdc0", "top_msdc50_0", 8),
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GATE_INFRA_AO3(CLK_INFRA_AO_MSDC30_2, "infra_ao_msdc30_2", "top_msdc30_2", 9),
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GATE_INFRA_AO3(CLK_INFRA_AO_GCPU, "infra_ao_gcpu", "top_gcpu", 10),
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GATE_INFRA_AO3(CLK_INFRA_AO_PCIE_PERI_26M, "infra_ao_pcie_peri_26m", "clk26m", 15),
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GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_66M_BCLK, "infra_ao_gcpu_66m_bclk", "top_axi", 16),
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GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_133M_BCLK, "infra_ao_gcpu_133m_bclk", "top_axi", 17),
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GATE_INFRA_AO3(CLK_INFRA_AO_DISP_PWM1, "infra_ao_disp_pwm1", "top_disp_pwm1", 20),
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GATE_INFRA_AO3(CLK_INFRA_AO_FBIST2FPC, "infra_ao_fbist2fpc", "top_msdc50_0", 24),
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/* infra_ao_dapc_sync is for device access permission control module */
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GATE_INFRA_AO3_FLAGS(CLK_INFRA_AO_DEVICE_APC_SYNC, "infra_ao_dapc_sync",
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"top_axi", 25, CLK_IS_CRITICAL),
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GATE_INFRA_AO3(CLK_INFRA_AO_PCIE_P1_PERI_26M, "infra_ao_pcie_p1_peri_26m", "clk26m", 26),
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/* INFRA_AO4 */
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/* infra_ao_133m_mclk_set/infra_ao_66m_mclk_set are main clocks of peripheral */
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GATE_INFRA_AO4_FLAGS(CLK_INFRA_AO_133M_MCLK_CK, "infra_ao_133m_mclk_set",
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"top_axi", 0, CLK_IS_CRITICAL),
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GATE_INFRA_AO4_FLAGS(CLK_INFRA_AO_66M_MCLK_CK, "infra_ao_66m_mclk_set",
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"top_axi", 1, CLK_IS_CRITICAL),
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GATE_INFRA_AO4(CLK_INFRA_AO_PCIE_PL_P_250M_P0, "infra_ao_pcie_pl_p_250m_p0",
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"pextp_pipe", 7),
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GATE_INFRA_AO4(CLK_INFRA_AO_RG_AES_MSDCFDE_CK_0P,
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"infra_ao_aes_msdcfde_0p", "top_aes_msdcfde", 18),
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};
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static const struct mtk_clk_desc infra_ao_desc = {
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.clks = infra_ao_clks,
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.num_clks = ARRAY_SIZE(infra_ao_clks),
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};
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static const struct of_device_id of_match_clk_mt8188_infra_ao[] = {
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{ .compatible = "mediatek,mt8188-infracfg-ao", .data = &infra_ao_desc },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_infra_ao);
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static struct platform_driver clk_mt8188_infra_ao_drv = {
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt8188-infra_ao",
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.of_match_table = of_match_clk_mt8188_infra_ao,
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},
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};
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module_platform_driver(clk_mt8188_infra_ao_drv);
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MODULE_LICENSE("GPL");

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