@@ -193,30 +193,29 @@ static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
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link -> clkpm_disable = blacklist ? 1 : 0 ;
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}
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- static bool pcie_retrain_link (struct pcie_link_state * link )
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+ static bool pcie_retrain_link (struct pci_dev * pdev )
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{
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- struct pci_dev * parent = link -> pdev ;
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unsigned long end_jiffies ;
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u16 lnkctl ;
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u16 lnksta ;
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- pcie_capability_read_word (parent , PCI_EXP_LNKCTL , & lnkctl );
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+ pcie_capability_read_word (pdev , PCI_EXP_LNKCTL , & lnkctl );
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lnkctl |= PCI_EXP_LNKCTL_RL ;
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- pcie_capability_write_word (parent , PCI_EXP_LNKCTL , lnkctl );
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- if (parent -> clear_retrain_link ) {
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+ pcie_capability_write_word (pdev , PCI_EXP_LNKCTL , lnkctl );
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+ if (pdev -> clear_retrain_link ) {
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/*
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* Due to an erratum in some devices the Retrain Link bit
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* needs to be cleared again manually to allow the link
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* training to succeed.
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*/
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lnkctl &= ~PCI_EXP_LNKCTL_RL ;
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- pcie_capability_write_word (parent , PCI_EXP_LNKCTL , lnkctl );
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+ pcie_capability_write_word (pdev , PCI_EXP_LNKCTL , lnkctl );
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}
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/* Wait for link training end. Break out after waiting for timeout */
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end_jiffies = jiffies + LINK_RETRAIN_TIMEOUT ;
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do {
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- pcie_capability_read_word (parent , PCI_EXP_LNKSTA , & lnksta );
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+ pcie_capability_read_word (pdev , PCI_EXP_LNKSTA , & lnksta );
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if (!(lnksta & PCI_EXP_LNKSTA_LT ))
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break ;
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msleep (1 );
@@ -290,7 +289,7 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
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reg16 &= ~PCI_EXP_LNKCTL_CCC ;
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pcie_capability_write_word (parent , PCI_EXP_LNKCTL , reg16 );
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- if (pcie_retrain_link (link ))
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+ if (pcie_retrain_link (link -> pdev ))
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return ;
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/* Training failed. Restore common clock configurations */
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