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Kenneth Fengalexdeucher
Kenneth Feng
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alexdeucher
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drm/amd/powerplay: read pcie speed/width info (v2)
sysfs interface to read pcie speed&width info on navi1x. v2: fix warning (trivial) Signed-off-by: Kenneth Feng <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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4 files changed

+69
-9
lines changed

‎drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1068,10 +1068,6 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
10681068
return ret;
10691069

10701070
if (adev->asic_type != CHIP_ARCTURUS) {
1071-
ret = smu_override_pcie_parameters(smu);
1072-
if (ret)
1073-
return ret;
1074-
10751071
ret = smu_notify_display_change(smu);
10761072
if (ret)
10771073
return ret;
@@ -1100,6 +1096,12 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
11001096
return ret;
11011097
}
11021098

1099+
if (adev->asic_type != CHIP_ARCTURUS) {
1100+
ret = smu_override_pcie_parameters(smu);
1101+
if (ret)
1102+
return ret;
1103+
}
1104+
11031105
ret = smu_set_default_od_settings(smu, initialize);
11041106
if (ret)
11051107
return ret;

‎drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,8 @@
4848

4949
#define SMU11_TOOL_SIZE 0x19000
5050

51+
#define MAX_PCIE_CONF 2
52+
5153
#define CLK_MAP(clk, index) \
5254
[SMU_##clk] = {1, (index)}
5355

@@ -88,6 +90,11 @@ struct smu_11_0_dpm_table {
8890
uint32_t max; /* MHz */
8991
};
9092

93+
struct smu_11_0_pcie_table {
94+
uint8_t pcie_gen[MAX_PCIE_CONF];
95+
uint8_t pcie_lane[MAX_PCIE_CONF];
96+
};
97+
9198
struct smu_11_0_dpm_tables {
9299
struct smu_11_0_dpm_table soc_table;
93100
struct smu_11_0_dpm_table gfx_table;
@@ -100,6 +107,7 @@ struct smu_11_0_dpm_tables {
100107
struct smu_11_0_dpm_table display_table;
101108
struct smu_11_0_dpm_table phy_table;
102109
struct smu_11_0_dpm_table fclk_table;
110+
struct smu_11_0_pcie_table pcie_table;
103111
};
104112

105113
struct smu_11_0_dpm_context {

‎drivers/gpu/drm/amd/powerplay/navi10_ppt.c

Lines changed: 52 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,7 @@
3636
#include "navi10_ppt.h"
3737
#include "smu_v11_0_pptable.h"
3838
#include "smu_v11_0_ppsmc.h"
39+
#include "nbio/nbio_7_4_sh_mask.h"
3940

4041
#include "asic_reg/mp/mp_11_0_sh_mask.h"
4142

@@ -599,6 +600,7 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
599600
struct smu_table_context *table_context = &smu->smu_table;
600601
struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
601602
PPTable_t *driver_ppt = NULL;
603+
int i;
602604

603605
driver_ppt = table_context->driver_pptable;
604606

@@ -629,6 +631,11 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
629631
dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
630632
dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
631633

634+
for (i = 0; i < MAX_PCIE_CONF; i++) {
635+
dpm_context->dpm_tables.pcie_table.pcie_gen[i] = driver_ppt->PcieGenSpeed[i];
636+
dpm_context->dpm_tables.pcie_table.pcie_lane[i] = driver_ppt->PcieLaneCount[i];
637+
}
638+
632639
return 0;
633640
}
634641

@@ -700,16 +707,20 @@ static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_tabl
700707
static int navi10_print_clk_levels(struct smu_context *smu,
701708
enum smu_clk_type clk_type, char *buf)
702709
{
703-
OverDriveTable_t *od_table;
704-
struct smu_11_0_overdrive_table *od_settings;
705710
uint16_t *curve_settings;
706711
int i, size = 0, ret = 0;
707712
uint32_t cur_value = 0, value = 0, count = 0;
708713
uint32_t freq_values[3] = {0};
709714
uint32_t mark_index = 0;
710715
struct smu_table_context *table_context = &smu->smu_table;
711-
od_table = (OverDriveTable_t *)table_context->overdrive_table;
712-
od_settings = smu->od_settings;
716+
uint32_t gen_speed, lane_width;
717+
struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
718+
struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
719+
struct amdgpu_device *adev = smu->adev;
720+
PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
721+
OverDriveTable_t *od_table =
722+
(OverDriveTable_t *)table_context->overdrive_table;
723+
struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
713724

714725
switch (clk_type) {
715726
case SMU_GFXCLK:
@@ -760,6 +771,30 @@ static int navi10_print_clk_levels(struct smu_context *smu,
760771

761772
}
762773
break;
774+
case SMU_PCIE:
775+
gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
776+
PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
777+
>> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
778+
lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
779+
PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
780+
>> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
781+
for (i = 0; i < NUM_LINK_LEVELS; i++)
782+
size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
783+
(dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
784+
(dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
785+
(dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
786+
(dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
787+
(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
788+
(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
789+
(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
790+
(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
791+
(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
792+
(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
793+
pptable->LclkFreq[i],
794+
(gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
795+
(lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
796+
"*" : "");
797+
break;
763798
case SMU_OD_SCLK:
764799
if (!smu->od_enabled || !od_table || !od_settings)
765800
break;
@@ -1690,6 +1725,9 @@ static int navi10_update_pcie_parameters(struct smu_context *smu,
16901725
int ret, i;
16911726
uint32_t smu_pcie_arg;
16921727

1728+
struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1729+
struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1730+
16931731
for (i = 0; i < NUM_LINK_LEVELS; i++) {
16941732
smu_pcie_arg = (i << 16) |
16951733
((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) :
@@ -1698,8 +1736,17 @@ static int navi10_update_pcie_parameters(struct smu_context *smu,
16981736
ret = smu_send_smc_msg_with_param(smu,
16991737
SMU_MSG_OverridePcieParameters,
17001738
smu_pcie_arg);
1739+
1740+
if (ret)
1741+
return ret;
1742+
1743+
if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
1744+
dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
1745+
if (pptable->PcieLaneCount[i] > pcie_width_cap)
1746+
dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
17011747
}
1702-
return ret;
1748+
1749+
return 0;
17031750
}
17041751

17051752
static inline void navi10_dump_od_table(OverDriveTable_t *od_table) {

‎drivers/gpu/drm/amd/powerplay/navi10_ppt.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -35,6 +35,9 @@
3535

3636
#define NAVI10_VOLTAGE_SCALE (4)
3737

38+
#define smnPCIE_LC_SPEED_CNTL 0x11140290
39+
#define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
40+
3841
extern void navi10_set_ppt_funcs(struct smu_context *smu);
3942

4043
#endif

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