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| 1 | +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)*/ |
| 2 | +/* |
| 3 | + * Copyright (c) 2022 MediaTek Inc. |
| 4 | + * Author: Runyang Chen <[email protected]> |
| 5 | + */ |
| 6 | + |
| 7 | +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8188 |
| 8 | +#define _DT_BINDINGS_RESET_CONTROLLER_MT8188 |
| 9 | + |
| 10 | +#define MT8188_TOPRGU_CONN_MCU_SW_RST 0 |
| 11 | +#define MT8188_TOPRGU_INFRA_GRST_SW_RST 1 |
| 12 | +#define MT8188_TOPRGU_IPU0_SW_RST 2 |
| 13 | +#define MT8188_TOPRGU_IPU1_SW_RST 3 |
| 14 | +#define MT8188_TOPRGU_IPU2_SW_RST 4 |
| 15 | +#define MT8188_TOPRGU_AUD_ASRC_SW_RST 5 |
| 16 | +#define MT8188_TOPRGU_INFRA_SW_RST 6 |
| 17 | +#define MT8188_TOPRGU_MMSYS_SW_RST 7 |
| 18 | +#define MT8188_TOPRGU_MFG_SW_RST 8 |
| 19 | +#define MT8188_TOPRGU_VENC_SW_RST 9 |
| 20 | +#define MT8188_TOPRGU_VDEC_SW_RST 10 |
| 21 | +#define MT8188_TOPRGU_CAM_VCORE_SW_RST 11 |
| 22 | +#define MT8188_TOPRGU_SCP_SW_RST 12 |
| 23 | +#define MT8188_TOPRGU_APMIXEDSYS_SW_RST 13 |
| 24 | +#define MT8188_TOPRGU_AUDIO_SW_RST 14 |
| 25 | +#define MT8188_TOPRGU_CAMSYS_SW_RST 15 |
| 26 | +#define MT8188_TOPRGU_MJC_SW_RST 16 |
| 27 | +#define MT8188_TOPRGU_PERI_SW_RST 17 |
| 28 | +#define MT8188_TOPRGU_PERI_AO_SW_RST 18 |
| 29 | +#define MT8188_TOPRGU_PCIE_SW_RST 19 |
| 30 | +#define MT8188_TOPRGU_ADSPSYS_SW_RST 21 |
| 31 | +#define MT8188_TOPRGU_DPTX_SW_RST 22 |
| 32 | +#define MT8188_TOPRGU_SPMI_MST_SW_RST 23 |
| 33 | + |
| 34 | +#define MT8188_TOPRGU_SW_RST_NUM 24 |
| 35 | + |
| 36 | +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */ |
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