|
92 | 92 | timeout-sec = <30>;
|
93 | 93 | };
|
94 | 94 |
|
| 95 | + v2m_clk24mhz: clk24mhz { |
| 96 | + compatible = "fixed-clock"; |
| 97 | + #clock-cells = <0>; |
| 98 | + clock-frequency = <24000000>; |
| 99 | + clock-output-names = "v2m:clk24mhz"; |
| 100 | + }; |
| 101 | + |
| 102 | + v2m_refclk1mhz: refclk1mhz { |
| 103 | + compatible = "fixed-clock"; |
| 104 | + #clock-cells = <0>; |
| 105 | + clock-frequency = <1000000>; |
| 106 | + clock-output-names = "v2m:refclk1mhz"; |
| 107 | + }; |
| 108 | + |
| 109 | + v2m_refclk32khz: refclk32khz { |
| 110 | + compatible = "fixed-clock"; |
| 111 | + #clock-cells = <0>; |
| 112 | + clock-frequency = <32768>; |
| 113 | + clock-output-names = "v2m:refclk32khz"; |
| 114 | + }; |
| 115 | + |
95 | 116 | bus@8000000 {
|
96 | 117 | compatible = "arm,vexpress,v2m-p1", "simple-bus";
|
97 | 118 | arm,v2m-memory-map = "rs1";
|
|
157 | 178 | interrupts = <15>;
|
158 | 179 | };
|
159 | 180 |
|
160 |
| - v2m_clk24mhz: clk24mhz { |
161 |
| - compatible = "fixed-clock"; |
162 |
| - #clock-cells = <0>; |
163 |
| - clock-frequency = <24000000>; |
164 |
| - clock-output-names = "v2m:clk24mhz"; |
165 |
| - }; |
166 |
| - |
167 |
| - v2m_refclk1mhz: refclk1mhz { |
168 |
| - compatible = "fixed-clock"; |
169 |
| - #clock-cells = <0>; |
170 |
| - clock-frequency = <1000000>; |
171 |
| - clock-output-names = "v2m:refclk1mhz"; |
172 |
| - }; |
173 |
| - |
174 |
| - v2m_refclk32khz: refclk32khz { |
175 |
| - compatible = "fixed-clock"; |
176 |
| - #clock-cells = <0>; |
177 |
| - clock-frequency = <32768>; |
178 |
| - clock-output-names = "v2m:refclk32khz"; |
179 |
| - }; |
180 |
| - |
181 | 181 | iofpga@300000000 {
|
182 | 182 | compatible = "simple-bus";
|
183 | 183 | #address-cells = <1>;
|
|
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