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jayxurockchiplinusw
jayxurockchip
authored and
linusw
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gpio/rockchip: use struct rockchip_gpio_regs for gpio controller
Store register offsets in the struct rockchip_gpio_regs, this patch prepare for the driver update for new gpio controller. Reviewed-by: Heiko Stuebner <[email protected]> Signed-off-by: Jianqun Xu <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
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+85
-39
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2 files changed

+85
-39
lines changed

‎drivers/gpio/gpio-rockchip.c

Lines changed: 47 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -24,27 +24,29 @@
2424
#include "../pinctrl/core.h"
2525
#include "../pinctrl/pinctrl-rockchip.h"
2626

27-
/* GPIO control registers */
28-
#define GPIO_SWPORT_DR 0x00
29-
#define GPIO_SWPORT_DDR 0x04
30-
#define GPIO_INTEN 0x30
31-
#define GPIO_INTMASK 0x34
32-
#define GPIO_INTTYPE_LEVEL 0x38
33-
#define GPIO_INT_POLARITY 0x3c
34-
#define GPIO_INT_STATUS 0x40
35-
#define GPIO_INT_RAWSTATUS 0x44
36-
#define GPIO_DEBOUNCE 0x48
37-
#define GPIO_PORTS_EOI 0x4c
38-
#define GPIO_EXT_PORT 0x50
39-
#define GPIO_LS_SYNC 0x60
27+
#define GPIO_TYPE_V1 (0) /* GPIO Version ID reserved */
28+
29+
static const struct rockchip_gpio_regs gpio_regs_v1 = {
30+
.port_dr = 0x00,
31+
.port_ddr = 0x04,
32+
.int_en = 0x30,
33+
.int_mask = 0x34,
34+
.int_type = 0x38,
35+
.int_polarity = 0x3c,
36+
.int_status = 0x40,
37+
.int_rawstatus = 0x44,
38+
.debounce = 0x48,
39+
.port_eoi = 0x4c,
40+
.ext_port = 0x50,
41+
};
4042

4143
static int rockchip_gpio_get_direction(struct gpio_chip *chip,
4244
unsigned int offset)
4345
{
4446
struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
4547
u32 data;
4648

47-
data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
49+
data = readl_relaxed(bank->reg_base + bank->gpio_regs->port_ddr);
4850
if (data & BIT(offset))
4951
return GPIO_LINE_DIRECTION_OUT;
5052

@@ -60,13 +62,13 @@ static int rockchip_gpio_set_direction(struct gpio_chip *chip,
6062

6163
raw_spin_lock_irqsave(&bank->slock, flags);
6264

63-
data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
65+
data = readl_relaxed(bank->reg_base + bank->gpio_regs->port_ddr);
6466
/* set bit to 1 for output, 0 for input */
6567
if (!input)
6668
data |= BIT(offset);
6769
else
6870
data &= ~BIT(offset);
69-
writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
71+
writel_relaxed(data, bank->reg_base + bank->gpio_regs->port_ddr);
7072

7173
raw_spin_unlock_irqrestore(&bank->slock, flags);
7274

@@ -77,7 +79,7 @@ static void rockchip_gpio_set(struct gpio_chip *gc, unsigned int offset,
7779
int value)
7880
{
7981
struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
80-
void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
82+
void __iomem *reg = bank->reg_base + bank->gpio_regs->port_dr;
8183
unsigned long flags;
8284
u32 data;
8385

@@ -97,17 +99,18 @@ static int rockchip_gpio_get(struct gpio_chip *gc, unsigned int offset)
9799
struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
98100
u32 data;
99101

100-
data = readl(bank->reg_base + GPIO_EXT_PORT);
102+
data = readl(bank->reg_base + bank->gpio_regs->ext_port);
101103
data >>= offset;
102104
data &= 1;
105+
103106
return data;
104107
}
105108

106109
static void rockchip_gpio_set_debounce(struct gpio_chip *gc,
107110
unsigned int offset, bool enable)
108111
{
109112
struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
110-
void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE;
113+
void __iomem *reg = bank->reg_base + bank->gpio_regs->debounce;
111114
unsigned long flags;
112115
u32 data;
113116

@@ -207,7 +210,7 @@ static void rockchip_irq_demux(struct irq_desc *desc)
207210

208211
chained_irq_enter(chip, desc);
209212

210-
pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
213+
pend = readl_relaxed(bank->reg_base + bank->gpio_regs->int_status);
211214

212215
while (pend) {
213216
unsigned int irq, virq;
@@ -231,24 +234,26 @@ static void rockchip_irq_demux(struct irq_desc *desc)
231234
u32 data, data_old, polarity;
232235
unsigned long flags;
233236

234-
data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
237+
data = readl_relaxed(bank->reg_base +
238+
bank->gpio_regs->ext_port);
235239
do {
236240
raw_spin_lock_irqsave(&bank->slock, flags);
237241

238242
polarity = readl_relaxed(bank->reg_base +
239-
GPIO_INT_POLARITY);
243+
bank->gpio_regs->int_polarity);
240244
if (data & BIT(irq))
241245
polarity &= ~BIT(irq);
242246
else
243247
polarity |= BIT(irq);
244248
writel(polarity,
245-
bank->reg_base + GPIO_INT_POLARITY);
249+
bank->reg_base +
250+
bank->gpio_regs->int_polarity);
246251

247252
raw_spin_unlock_irqrestore(&bank->slock, flags);
248253

249254
data_old = data;
250255
data = readl_relaxed(bank->reg_base +
251-
GPIO_EXT_PORT);
256+
bank->gpio_regs->ext_port);
252257
} while ((data & BIT(irq)) != (data_old & BIT(irq)));
253258
}
254259

@@ -270,9 +275,9 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
270275

271276
raw_spin_lock_irqsave(&bank->slock, flags);
272277

273-
data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
278+
data = readl_relaxed(bank->reg_base + bank->gpio_regs->port_ddr);
274279
data &= ~mask;
275-
writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
280+
writel_relaxed(data, bank->reg_base + bank->gpio_regs->port_ddr);
276281

277282
raw_spin_unlock_irqrestore(&bank->slock, flags);
278283

@@ -284,8 +289,8 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
284289
raw_spin_lock_irqsave(&bank->slock, flags);
285290
irq_gc_lock(gc);
286291

287-
level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
288-
polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
292+
level = readl_relaxed(gc->reg_base + bank->gpio_regs->int_type);
293+
polarity = readl_relaxed(gc->reg_base + bank->gpio_regs->int_polarity);
289294

290295
switch (type) {
291296
case IRQ_TYPE_EDGE_BOTH:
@@ -296,7 +301,7 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
296301
* Determine gpio state. If 1 next interrupt should be falling
297302
* otherwise rising.
298303
*/
299-
data = readl(bank->reg_base + GPIO_EXT_PORT);
304+
data = readl(bank->reg_base + bank->gpio_regs->ext_port);
300305
if (data & mask)
301306
polarity &= ~mask;
302307
else
@@ -329,8 +334,8 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
329334
return -EINVAL;
330335
}
331336

332-
writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
333-
writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
337+
writel_relaxed(level, gc->reg_base + bank->gpio_regs->int_type);
338+
writel_relaxed(polarity, gc->reg_base + bank->gpio_regs->int_polarity);
334339

335340
irq_gc_unlock(gc);
336341
raw_spin_unlock_irqrestore(&bank->slock, flags);
@@ -343,16 +348,16 @@ static void rockchip_irq_suspend(struct irq_data *d)
343348
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
344349
struct rockchip_pin_bank *bank = gc->private;
345350

346-
bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
347-
irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
351+
bank->saved_masks = irq_reg_readl(gc, bank->gpio_regs->int_mask);
352+
irq_reg_writel(gc, ~gc->wake_active, bank->gpio_regs->int_mask);
348353
}
349354

350355
static void rockchip_irq_resume(struct irq_data *d)
351356
{
352357
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
353358
struct rockchip_pin_bank *bank = gc->private;
354359

355-
irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
360+
irq_reg_writel(gc, bank->saved_masks, bank->gpio_regs->int_mask);
356361
}
357362

358363
static void rockchip_irq_enable(struct irq_data *d)
@@ -400,8 +405,8 @@ static int rockchip_interrupts_register(struct rockchip_pin_bank *bank)
400405
gc = irq_get_domain_generic_chip(bank->domain, 0);
401406
gc->reg_base = bank->reg_base;
402407
gc->private = bank;
403-
gc->chip_types[0].regs.mask = GPIO_INTMASK;
404-
gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
408+
gc->chip_types[0].regs.mask = bank->gpio_regs->int_mask;
409+
gc->chip_types[0].regs.ack = bank->gpio_regs->port_eoi;
405410
gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
406411
gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
407412
gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
@@ -418,9 +423,9 @@ static int rockchip_interrupts_register(struct rockchip_pin_bank *bank)
418423
* Our driver only uses the concept of masked and always keeps
419424
* things enabled, so for us that's all masked and all enabled.
420425
*/
421-
writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
422-
writel_relaxed(0xffffffff, bank->reg_base + GPIO_PORTS_EOI);
423-
writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
426+
writel_relaxed(0xffffffff, bank->reg_base + bank->gpio_regs->int_mask);
427+
writel_relaxed(0xffffffff, bank->reg_base + bank->gpio_regs->port_eoi);
428+
writel_relaxed(0xffffffff, bank->reg_base + bank->gpio_regs->int_en);
424429
gc->mask_cache = 0xffffffff;
425430

426431
irq_set_chained_handler_and_data(bank->irq,
@@ -510,6 +515,9 @@ static int rockchip_get_bank_data(struct rockchip_pin_bank *bank)
510515

511516
bank->irq = irq_of_parse_and_map(bank->of_node, 0);
512517

518+
bank->gpio_regs = &gpio_regs_v1;
519+
bank->gpio_type = GPIO_TYPE_V1;
520+
513521
bank->clk = of_clk_get(bank->of_node, 0);
514522
if (!IS_ERR(bank->clk))
515523
return clk_prepare_enable(bank->clk);

‎drivers/pinctrl/pinctrl-rockchip.h

Lines changed: 38 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,42 @@ enum rockchip_pinctrl_type {
3232
RK3568,
3333
};
3434

35+
/**
36+
* struct rockchip_gpio_regs
37+
* @port_dr: data register
38+
* @port_ddr: data direction register
39+
* @int_en: interrupt enable
40+
* @int_mask: interrupt mask
41+
* @int_type: interrupt trigger type, such as high, low, edge trriger type.
42+
* @int_polarity: interrupt polarity enable register
43+
* @int_bothedge: interrupt bothedge enable register
44+
* @int_status: interrupt status register
45+
* @int_rawstatus: int_status = int_rawstatus & int_mask
46+
* @debounce: enable debounce for interrupt signal
47+
* @dbclk_div_en: enable divider for debounce clock
48+
* @dbclk_div_con: setting for divider of debounce clock
49+
* @port_eoi: end of interrupt of the port
50+
* @ext_port: port data from external
51+
* @version_id: controller version register
52+
*/
53+
struct rockchip_gpio_regs {
54+
u32 port_dr;
55+
u32 port_ddr;
56+
u32 int_en;
57+
u32 int_mask;
58+
u32 int_type;
59+
u32 int_polarity;
60+
u32 int_bothedge;
61+
u32 int_status;
62+
u32 int_rawstatus;
63+
u32 debounce;
64+
u32 dbclk_div_en;
65+
u32 dbclk_div_con;
66+
u32 port_eoi;
67+
u32 ext_port;
68+
u32 version_id;
69+
};
70+
3571
/**
3672
* struct rockchip_iomux
3773
* @type: iomux variant using IOMUX_* constants
@@ -126,6 +162,8 @@ struct rockchip_pin_bank {
126162
struct gpio_chip gpio_chip;
127163
struct pinctrl_gpio_range grange;
128164
raw_spinlock_t slock;
165+
const struct rockchip_gpio_regs *gpio_regs;
166+
u32 gpio_type;
129167
u32 toggle_edge_mode;
130168
u32 recalced_mask;
131169
u32 route_mask;

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