Skip to content

Commit ffcdf47

Browse files
parakatsbogend
authored andcommitted
mips: ralink: rt288x: remove clock related code
A properly clock driver for ralink SoCs has been added. Hence there is no need to have clock related code in 'arch/mips/ralink' folder anymore. Signed-off-by: Sergio Paracuellos <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
1 parent 6f3b155 commit ffcdf47

File tree

2 files changed

+0
-41
lines changed

2 files changed

+0
-41
lines changed

arch/mips/include/asm/mach-ralink/rt288x.h

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,6 @@
1818
#define SYSC_REG_CHIP_NAME1 0x04
1919
#define SYSC_REG_CHIP_ID 0x0c
2020
#define SYSC_REG_SYSTEM_CONFIG 0x10
21-
#define SYSC_REG_CLKCFG 0x30
2221

2322
#define RT2880_CHIP_NAME0 0x38325452
2423
#define RT2880_CHIP_NAME1 0x20203038
@@ -27,15 +26,6 @@
2726
#define CHIP_ID_ID_SHIFT 8
2827
#define CHIP_ID_REV_MASK 0xff
2928

30-
#define SYSTEM_CONFIG_CPUCLK_SHIFT 20
31-
#define SYSTEM_CONFIG_CPUCLK_MASK 0x3
32-
#define SYSTEM_CONFIG_CPUCLK_250 0x0
33-
#define SYSTEM_CONFIG_CPUCLK_266 0x1
34-
#define SYSTEM_CONFIG_CPUCLK_280 0x2
35-
#define SYSTEM_CONFIG_CPUCLK_300 0x3
36-
37-
#define CLKCFG_SRAM_CS_N_WDT BIT(9)
38-
3929
#define RT2880_SDRAM_BASE 0x08000000
4030
#define RT2880_MEM_SIZE_MIN 2
4131
#define RT2880_MEM_SIZE_MAX 128

arch/mips/ralink/rt288x.c

Lines changed: 0 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -21,37 +21,6 @@
2121

2222
static struct ralink_soc_info *soc_info_ptr;
2323

24-
void __init ralink_clk_init(void)
25-
{
26-
unsigned long cpu_rate, wmac_rate = 40000000;
27-
u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
28-
t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
29-
30-
switch (t) {
31-
case SYSTEM_CONFIG_CPUCLK_250:
32-
cpu_rate = 250000000;
33-
break;
34-
case SYSTEM_CONFIG_CPUCLK_266:
35-
cpu_rate = 266666667;
36-
break;
37-
case SYSTEM_CONFIG_CPUCLK_280:
38-
cpu_rate = 280000000;
39-
break;
40-
case SYSTEM_CONFIG_CPUCLK_300:
41-
cpu_rate = 300000000;
42-
break;
43-
}
44-
45-
ralink_clk_add("cpu", cpu_rate);
46-
ralink_clk_add("300100.timer", cpu_rate / 2);
47-
ralink_clk_add("300120.watchdog", cpu_rate / 2);
48-
ralink_clk_add("300500.uart", cpu_rate / 2);
49-
ralink_clk_add("300900.i2c", cpu_rate / 2);
50-
ralink_clk_add("300c00.uartlite", cpu_rate / 2);
51-
ralink_clk_add("400000.ethernet", cpu_rate / 2);
52-
ralink_clk_add("480000.wmac", wmac_rate);
53-
}
54-
5524
void __init ralink_of_remap(void)
5625
{
5726
rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc");

0 commit comments

Comments
 (0)