Merge pull request #2146 from SAP/pr-jdk-27+3

Merge to tag jdk-27+3

Author: RealCLanger

README.md

@@ -3,21 +3,21 @@
 <img align="right" width=350 src="https://sapmachine.io/assets/images/logo_circular.svg">
 
 # [](#SapMachine) SapMachine
-SapMachine is a downstream fork of the [OpenJDK](https://openjdk.org/) project. Its purpose is to build and support a binary distribution of OpenJDK for SAP customers and partners.
+SapMachine is a downstream fork of the [OpenJDK](https://openjdk.org/) project, aimed at providing a binary distribution of OpenJDK for SAP customers and partners.
 
-While maintaining SapMachine, SAP is committed to ensuring the continued success of the Java platform and the OpenJDK project and therefore works in an OpenJDK-upstream-first model. To learn more about our engagement in the OpenJDK, visit [this site](https://sapmachine.io/docs/sap-in-openjdk).
+SAP is committed to the ongoing success of the Java platform and the OpenJDK project, maintaining SapMachine in an OpenJDK-upstream-first model. Additional information regarding SAP's engagement in OpenJDK is available on the [SAP OpenJDK Engagement page](https://sapmachine.io/docs/sap-in-openjdk).
 
-More details about SapMachine, such as *installation instructions*, *frequently asked questions*, *the maintenance and support statement*, and more are available in the [documentation pages](https://sapmachine.io/docs).
+Further details about SapMachine, including *installation instructions*, *frequently asked questions*, *the maintenance and support statement*, can be found on the [documentation pages](https://sapmachine.io/docs).
 
-## Have an issue?
-If it's SapMachine specific please let us know by filing a [new issue](https://github.com/SAP/SapMachine/issues/new).
+## Issues
+For SapMachine-specific concerns, please file a [new issue](https://github.com/SAP/SapMachine/issues/new).
 
-General JVM/JDK bugs are maintained directly in the [OpenJDK Bug System](https://bugs.openjdk.org/). You can open a SapMachine issue with a reference to an open or resolved OpenJDK bug if you want us to resolve the issue or downport the fix to a specific SapMachine version. If you find a general JVM/JDK bug in SapMachine and don't have editor access to the OpenJDK Bug System you can open an issue here and we'll take care to open a corresponding OpenJDK bug for it.
+General JVM/JDK bugs are managed in the [OpenJDK Bug System](https://bugs.openjdk.org/). A SapMachine issue can be opened with reference to an existing OpenJDK bug for requesting resolution or backporting the fix to a specific SapMachine version. If a general JVM/JDK bug is found in SapMachine without editor access to the OpenJDK Bug System, an issue can be opened here, and a corresponding OpenJDK bug will be filed by us.
 
-Since SapMachine tracks the OpenJDK, every SapMachine release contains all the fixes/changes of the corresponding OpenJDK release it is based on.
+Since SapMachine tracks the OpenJDK, every SapMachine release contains all the fixes/changes of the corresponding OpenJDK release on which it is based.
 
 ## Contributing
-We currently do not accept external contributions for this project. If you want to improve the code or fix a bug please consider contributing directly to the upstream [OpenJDK](https://openjdk.org/contribute/) project. Our repositories will be regularly synced with OpenJDK, so any improvements in upstream will become effective in SapMachine as well.
+External contributions to this project are currently not accepted. For code improvements or bug fixes, contributions should be directed to the upstream [OpenJDK](https://openjdk.org/contribute/) project. Repositories are regularly synced with OpenJDK, ensuring that upstream improvements are realized in SapMachine.
 
 ## License
-This project is run under the same licensing terms as the upstream OpenJDK project. Please see the [LICENSE](LICENSE) file in the top-level directory for more information.
+This project is run under the same licensing terms as the upstream OpenJDK project. Additional information is available in the [LICENSE](LICENSE) file in the top-level directory.

make/autoconf/flags-ldflags.m4

@@ -63,15 +63,15 @@ AC_DEFUN([FLAGS_SETUP_LDFLAGS_HELPER],
     fi
 
     BASIC_LDFLAGS_JVM_ONLY=""
-    LDFLAGS_LTO="-flto=auto -fuse-linker-plugin -fno-strict-aliasing"
+    LDFLAGS_LTO="-flto=auto -fuse-linker-plugin -fno-strict-aliasing $DEBUG_PREFIX_CFLAGS"
 
     LDFLAGS_CXX_PARTIAL_LINKING="$MACHINE_FLAG -r"
 
   elif test "x$TOOLCHAIN_TYPE" = xclang; then
     BASIC_LDFLAGS_JVM_ONLY="-mno-omit-leaf-frame-pointer -mstack-alignment=16 \
         -fPIC"
 
-    LDFLAGS_LTO="-flto=auto -fuse-linker-plugin -fno-strict-aliasing"
+    LDFLAGS_LTO="-flto=auto -fuse-linker-plugin -fno-strict-aliasing $DEBUG_PREFIX_CFLAGS"
     LDFLAGS_CXX_PARTIAL_LINKING="$MACHINE_FLAG -r"
 
     if test "x$OPENJDK_TARGET_OS" = xlinux; then

make/modules/java.desktop/lib/ClientLibraries.gmk

@@ -226,6 +226,7 @@ ifeq ($(ENABLE_HEADLESS_ONLY), false)
       EXCLUDE_FILES := imageioJPEG.c jpegdecoder.c pngtest.c, \
       EXCLUDES := $(LIBSPLASHSCREEN_EXCLUDES), \
       OPTIMIZATION := SIZE, \
+      LINK_TIME_OPTIMIZATION := true, \
       CFLAGS := $(LIBSPLASHSCREEN_CFLAGS) \
           $(GIFLIB_CFLAGS) $(LIBJPEG_CFLAGS) $(PNG_CFLAGS) $(LIBZ_CFLAGS) \
           $(ICONV_CFLAGS), \

src/hotspot/cpu/aarch64/c1_Runtime1_aarch64.cpp

@@ -310,7 +310,18 @@ static void restore_live_registers(StubAssembler* sasm, bool restore_fpu_registe
     __ add(sp, sp, 32 * wordSize);
   }
 
+#ifdef R18_RESERVED
+  /*
+  Do not modify r18_tls when restoring registers if it is a reserved register. On Windows,
+  for example, r18_tls is used to store the pointer to the current thread's TEB (where TLS
+  variables are stored). Therefore, modifying r18_tls would corrupt the TEB pointer.
+  */
+  __ pop(RegSet::range(r0, r17), sp);
+  __ ldp(zr, r19, Address(__ post(sp, 2 * wordSize)));
+  __ pop(RegSet::range(r20, r29), sp);
+#else
   __ pop(RegSet::range(r0, r29), sp);
+#endif
 }
 
 static void restore_live_registers_except_r0(StubAssembler* sasm, bool restore_fpu_registers = true)  {
@@ -323,8 +334,20 @@ static void restore_live_registers_except_r0(StubAssembler* sasm, bool restore_f
     __ add(sp, sp, 32 * wordSize);
   }
 
+#ifdef R18_RESERVED
+  /*
+  Do not modify r18_tls when restoring registers if it is a reserved register. On Windows,
+  for example, r18_tls is used to store the pointer to the current thread's TEB (where TLS
+  variables are stored). Therefore, modifying r18_tls would corrupt the TEB pointer.
+  */
+  __ ldp(zr, r1, Address(__ post(sp, 2 * wordSize)));
+  __ pop(RegSet::range(r2, r17), sp);
+  __ ldp(zr, r19, Address(__ post(sp, 2 * wordSize)));
+  __ pop(RegSet::range(r20, r29), sp);
+#else
   __ ldp(zr, r1, Address(__ post(sp, 16)));
   __ pop(RegSet::range(r2, r29), sp);
+#endif
 }
 
 

src/hotspot/cpu/riscv/assembler_riscv.hpp

@@ -2662,6 +2662,9 @@ enum Nf {
   INSN(vsha2ch_vv,  0b1110111, 0b010, 0b1, 0b101110);
   INSN(vsha2cl_vv,  0b1110111, 0b010, 0b1, 0b101111);
 
+  // Vector GHASH (Zvkg) Extension
+  INSN(vghsh_vv,    0b1110111, 0b010, 0b1, 0b101100);
+
 #undef INSN
 
 #define INSN(NAME, op, funct3, Vs1, funct6)                                    \

src/hotspot/cpu/riscv/globals_riscv.hpp

@@ -123,6 +123,7 @@ define_pd_global(intx, InlineSmallCode,          1000);
   product(bool, UseZvkn, false, EXPERIMENTAL,                                    \
           "Use Zvkn group extension, Zvkned, Zvknhb, Zvkb, Zvkt")                \
   product(bool, UseCtxFencei, false, EXPERIMENTAL,                               \
-          "Use PR_RISCV_CTX_SW_FENCEI_ON to avoid explicit icache flush")
+          "Use PR_RISCV_CTX_SW_FENCEI_ON to avoid explicit icache flush")        \
+  product(bool, UseZvkg, false, EXPERIMENTAL, "Use Zvkg instructions")
 
 #endif // CPU_RISCV_GLOBALS_RISCV_HPP

src/hotspot/cpu/riscv/stubGenerator_riscv.cpp

@@ -2655,8 +2655,7 @@ class StubGenerator: public StubCodeGenerator {
   //   x10       - input length
   //
   address generate_cipherBlockChaining_encryptAESCrypt() {
-    assert(UseAESIntrinsics, "Must be");
-    assert(UseZvkn, "need AES instructions (Zvkned extension) support");
+    assert(UseAESIntrinsics, "need AES instructions (Zvkned extension) support");
     __ align(CodeEntryAlignment);
     StubId stub_id = StubId::stubgen_cipherBlockChaining_encryptAESCrypt_id;
     StubCodeMark mark(this, stub_id);
@@ -2745,8 +2744,7 @@ class StubGenerator: public StubCodeGenerator {
   //   x10       - input length
   //
   address generate_cipherBlockChaining_decryptAESCrypt() {
-    assert(UseAESIntrinsics, "Must be");
-    assert(UseZvkn, "need AES instructions (Zvkned extension) support");
+    assert(UseAESIntrinsics, "need AES instructions (Zvkned extension) support");
     __ align(CodeEntryAlignment);
     StubId stub_id = StubId::stubgen_cipherBlockChaining_decryptAESCrypt_id;
     StubCodeMark mark(this, stub_id);
@@ -2950,9 +2948,7 @@ class StubGenerator: public StubCodeGenerator {
   //   x10       - input length
   //
   address generate_counterMode_AESCrypt() {
-    assert(UseAESCTRIntrinsics, "Must be");
-    assert(UseZvkn, "need AES instructions (Zvkned extension) support");
-    assert(UseZbb, "need basic bit manipulation (Zbb extension) support");
+    assert(UseAESCTRIntrinsics, "need AES instructions (Zvkned extension) and Zbb extension support");
 
     __ align(CodeEntryAlignment);
     StubId stub_id = StubId::stubgen_counterMode_AESCrypt_id;
@@ -3001,6 +2997,63 @@ class StubGenerator: public StubCodeGenerator {
     return start;
   }
 
+  /**
+   *  Arguments:
+   *
+   *  Input:
+   *  c_rarg0   - current state address
+   *  c_rarg1   - H key address
+   *  c_rarg2   - data address
+   *  c_rarg3   - number of blocks
+   *
+   *  Output:
+   *  Updated state at c_rarg0
+   */
+  address generate_ghash_processBlocks() {
+    assert(UseGHASHIntrinsics, "need GHASH instructions (Zvkg extension) and Zvbb support");
+
+    __ align(CodeEntryAlignment);
+    StubId stub_id = StubId::stubgen_ghash_processBlocks_id;
+    StubCodeMark mark(this, stub_id);
+
+    address start = __ pc();
+    __ enter();
+
+    Register state   = c_rarg0;
+    Register subkeyH = c_rarg1;
+    Register data    = c_rarg2;
+    Register blocks  = c_rarg3;
+
+    VectorRegister partial_hash = v1;
+    VectorRegister hash_subkey  = v2;
+    VectorRegister cipher_text  = v3;
+
+    const unsigned int BLOCK_SIZE = 16;
+
+    __ vsetivli(x0, 2, Assembler::e64, Assembler::m1);
+    __ vle64_v(hash_subkey, subkeyH);
+    __ vrev8_v(hash_subkey, hash_subkey);
+    __ vle64_v(partial_hash, state);
+    __ vrev8_v(partial_hash, partial_hash);
+
+    __ vsetivli(x0, 4, Assembler::e32, Assembler::m1);
+    Label L_ghash_loop;
+    __ bind(L_ghash_loop);
+      __ vle32_v(cipher_text, data);
+      __ addi(data, data, BLOCK_SIZE);
+      __ vghsh_vv(partial_hash, hash_subkey, cipher_text);
+      __ subi(blocks, blocks, 1);
+      __ bnez(blocks, L_ghash_loop);
+
+    __ vsetivli(x0, 2, Assembler::e64, Assembler::m1);
+    __ vrev8_v(partial_hash, partial_hash);
+    __ vse64_v(partial_hash, state);
+    __ leave();
+    __ ret();
+
+    return start;
+  }
+
   // code for comparing 8 characters of strings with Latin1 and Utf16 encoding
   void compare_string_8_x_LU(Register tmpL, Register tmpU,
                              Register strL, Register strU, Label& DIFF) {
@@ -7227,6 +7280,10 @@ static const int64_t right_3_bits = right_n_bits(3);
       StubRoutines::_counterMode_AESCrypt = generate_counterMode_AESCrypt();
     }
 
+    if (UseGHASHIntrinsics) {
+      StubRoutines::_ghash_processBlocks = generate_ghash_processBlocks();
+    }
+
     if (UsePoly1305Intrinsics) {
       StubRoutines::_poly1305_processBlocks = generate_poly1305_processBlocks();
     }

src/hotspot/cpu/riscv/vm_version_riscv.cpp

@@ -457,6 +457,22 @@ void VM_Version::c2_initialize() {
       FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
     }
   }
+
+  if (UseZvkg) {
+    if (FLAG_IS_DEFAULT(UseGHASHIntrinsics) && UseZvbb) {
+      FLAG_SET_DEFAULT(UseGHASHIntrinsics, true);
+    }
+
+    if (UseGHASHIntrinsics && !UseZvbb) {
+      warning("Cannot enable UseGHASHIntrinsics on cpu without UseZvbb support");
+      FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
+    }
+  } else {
+    if (UseGHASHIntrinsics) {
+      warning("Cannot enable UseGHASHIntrinsics on cpu without UseZvkg support");
+      FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
+    }
+  }
 }
 
 #endif // COMPILER2

src/hotspot/cpu/riscv/vm_version_riscv.hpp

@@ -289,6 +289,8 @@ class VM_Version : public Abstract_VM_Version {
   decl(Zvfh        ,  RV_NO_FLAG_BIT,  true ,  UPDATE_DEFAULT_DEP(UseZvfh, &ext_v, &ext_Zfh, nullptr)) \
   /* Shorthand for Zvkned + Zvknhb + Zvkb + Zvkt */                                                    \
   decl(Zvkn        ,  RV_NO_FLAG_BIT,  true ,  UPDATE_DEFAULT_DEP(UseZvkn, &ext_v, nullptr))           \
+  /* Zvkg crypto extension for ghash and gcm */                                                        \
+  decl(Zvkg        ,  RV_NO_FLAG_BIT,  true ,  UPDATE_DEFAULT_DEP(UseZvkg, &ext_v, nullptr))           \
 
   #define DECLARE_RV_EXT_FEATURE(PRETTY, LINUX_BIT, FSTRING, FLAGF)                             \
   struct ext_##PRETTY##RVExtFeatureValue : public RVExtFeatureValue {                           \

src/hotspot/cpu/x86/assembler_x86.hpp

@@ -449,8 +449,8 @@ const int FPUStateSizeInWords = 2688 / wordSize;
 // imm8[1:0]                =  00 (min) / 01 (max)
 //
 // [1] https://www.intel.com/content/www/us/en/content-details/856721/intel-advanced-vector-extensions-10-2-intel-avx10-2-architecture-specification.html?wapkw=AVX10
-const int AVX10_MINMAX_MAX_COMPARE_SIGN = 0x5;
-const int AVX10_MINMAX_MIN_COMPARE_SIGN = 0x4;
+const int AVX10_2_MINMAX_MAX_COMPARE_SIGN = 0x5;
+const int AVX10_2_MINMAX_MIN_COMPARE_SIGN = 0x4;
 
 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write