From 19a97ac59910abb18725f23729db0a1281e726f0 Mon Sep 17 00:00:00 2001 From: Howard Su Date: Sat, 31 Aug 2019 05:53:59 -0700 Subject: [PATCH 1/2] CSR addr is only 12bits --- rtl/e203/core/e203_exu_alu_csrctrl.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rtl/e203/core/e203_exu_alu_csrctrl.v b/rtl/e203/core/e203_exu_alu_csrctrl.v index cee20ccc..06d17d7b 100644 --- a/rtl/e203/core/e203_exu_alu_csrctrl.v +++ b/rtl/e203/core/e203_exu_alu_csrctrl.v @@ -54,7 +54,7 @@ module e203_exu_alu_csrctrl( input eai_xs_off, output eai_csr_valid, input eai_csr_ready, - output [31:0] eai_csr_addr, + output [11:0] eai_csr_addr, output eai_csr_wr, output [31:0] eai_csr_wdata, input [31:0] eai_csr_rdata, From 1fe5e329db9a12d4f30188722c11ade637c5fbae Mon Sep 17 00:00:00 2001 From: Howard Su Date: Sat, 31 Aug 2019 06:19:57 -0700 Subject: [PATCH 2/2] Add CSR related defines CSR Addr is 12bits, E203_CSR_ADDR_W CSR Data is 32bits, E203_XLEN --- rtl/e203/core/e203_core.v | 6 +++--- rtl/e203/core/e203_cpu.v | 6 +++--- rtl/e203/core/e203_defines.v | 2 ++ rtl/e203/core/e203_extend_csr.v | 6 +++--- rtl/e203/core/e203_exu.v | 6 +++--- rtl/e203/core/e203_exu_alu.v | 6 +++--- rtl/e203/core/e203_exu_alu_csrctrl.v | 6 +++--- rtl/e203/core/e203_exu_csr.v | 2 +- 8 files changed, 21 insertions(+), 19 deletions(-) diff --git a/rtl/e203/core/e203_core.v b/rtl/e203/core/e203_core.v index 5264dd5b..6e754fcf 100644 --- a/rtl/e203/core/e203_core.v +++ b/rtl/e203/core/e203_core.v @@ -33,10 +33,10 @@ module e203_core( `ifdef E203_HAS_CSR_EAI//{ output eai_csr_valid, input eai_csr_ready, - output [31:0] eai_csr_addr, + output [`E203_CSR_ADDR_W-1:0] eai_csr_addr, output eai_csr_wr, - output [31:0] eai_csr_wdata, - input [31:0] eai_csr_rdata, + output [`E203_XLEN-1:0] eai_csr_wdata, + input [`E203_XLEN-1:0] eai_csr_rdata, `endif//} output core_wfi, output tm_stop, diff --git a/rtl/e203/core/e203_cpu.v b/rtl/e203/core/e203_cpu.v index 15cfb831..fa3c7d26 100644 --- a/rtl/e203/core/e203_cpu.v +++ b/rtl/e203/core/e203_cpu.v @@ -440,10 +440,10 @@ module e203_cpu #( `ifdef E203_HAS_CSR_EAI//{ wire eai_csr_valid; wire eai_csr_ready; - wire [31:0] eai_csr_addr; + wire [`E203_CSR_ADDR_W-1:0] eai_csr_addr; wire eai_csr_wr; - wire [31:0] eai_csr_wdata; - wire [31:0] eai_csr_rdata; + wire [`E203_XLEN-1:0] eai_csr_wdata; + wire [`E203_XLEN-1:0] eai_csr_rdata; // This is an empty module to just connect the EAI CSR interface, // user can hack it to become a real one diff --git a/rtl/e203/core/e203_defines.v b/rtl/e203/core/e203_defines.v index cd3cacb6..4b6dcb45 100644 --- a/rtl/e203/core/e203_defines.v +++ b/rtl/e203/core/e203_defines.v @@ -70,6 +70,8 @@ `define E203_INSTR_SIZE 32 +`define E203_CSR_ADDR_W 12 + // `define E203_RFIDX_WIDTH 5 `ifdef E203_CFG_REGNUM_IS_32//{ diff --git a/rtl/e203/core/e203_extend_csr.v b/rtl/e203/core/e203_extend_csr.v index 0f323caf..7263f89d 100644 --- a/rtl/e203/core/e203_extend_csr.v +++ b/rtl/e203/core/e203_extend_csr.v @@ -35,10 +35,10 @@ module e203_extend_csr( input eai_csr_valid, output eai_csr_ready, - input [31:0] eai_csr_addr, + input [`E203_CSR_ADDR_W-1:0] eai_csr_addr, input eai_csr_wr, - input [31:0] eai_csr_wdata, - output [31:0] eai_csr_rdata, + input [`E203_XLEN-1:0] eai_csr_wdata, + output [`E203_XLEN-1:0] eai_csr_rdata, input clk, input rst_n diff --git a/rtl/e203/core/e203_exu.v b/rtl/e203/core/e203_exu.v index 95ac8f11..bcd518c1 100644 --- a/rtl/e203/core/e203_exu.v +++ b/rtl/e203/core/e203_exu.v @@ -166,10 +166,10 @@ module e203_exu( `ifdef E203_HAS_CSR_EAI//{ output eai_csr_valid, input eai_csr_ready, - output [31:0] eai_csr_addr, + output [`E203_CSR_ADDR_W-1:0] eai_csr_addr, output eai_csr_wr, - output [31:0] eai_csr_wdata, - input [31:0] eai_csr_rdata, + output [`E203_XLEN-1:0] eai_csr_wdata, + input [`E203_XLEN-1:0] eai_csr_rdata, `endif//} diff --git a/rtl/e203/core/e203_exu_alu.v b/rtl/e203/core/e203_exu_alu.v index 33c79607..862c70a4 100644 --- a/rtl/e203/core/e203_exu_alu.v +++ b/rtl/e203/core/e203_exu_alu.v @@ -45,10 +45,10 @@ module e203_exu_alu( `endif// output eai_csr_valid, input eai_csr_ready, - output [31:0] eai_csr_addr, + output [`E203_CSR_ADDR_W-1:0] eai_csr_addr, output eai_csr_wr, - output [31:0] eai_csr_wdata, - input [31:0] eai_csr_rdata, + output [`E203_XLEN-1:0] eai_csr_wdata, + input [`E203_XLEN-1:0] eai_csr_rdata, `endif//} output amo_wait, diff --git a/rtl/e203/core/e203_exu_alu_csrctrl.v b/rtl/e203/core/e203_exu_alu_csrctrl.v index 06d17d7b..e822a052 100644 --- a/rtl/e203/core/e203_exu_alu_csrctrl.v +++ b/rtl/e203/core/e203_exu_alu_csrctrl.v @@ -54,10 +54,10 @@ module e203_exu_alu_csrctrl( input eai_xs_off, output eai_csr_valid, input eai_csr_ready, - output [11:0] eai_csr_addr, + output [`E203_CSR_ADDR_W-1:0] eai_csr_addr, output eai_csr_wr, - output [31:0] eai_csr_wdata, - input [31:0] eai_csr_rdata, + output [`E203_XLEN-1:0] eai_csr_wdata, + input [`E203_XLEN-1:0] eai_csr_rdata, `endif//} diff --git a/rtl/e203/core/e203_exu_csr.v b/rtl/e203/core/e203_exu_csr.v index 06602a67..a6eb604a 100644 --- a/rtl/e203/core/e203_exu_csr.v +++ b/rtl/e203/core/e203_exu_csr.v @@ -33,7 +33,7 @@ module e203_exu_csr( input csr_ena, input csr_wr_en, input csr_rd_en, - input [12-1:0] csr_idx, + input [`E203_CSR_ADDR_W-1:0] csr_idx, output csr_access_ilgl, output tm_stop,