Asynchronous_Core.v

`timescale 1ns / 1ps

module Asynchronous_Core(
    input Reset,
    
    output [31:0] out, reg0 /*, reg1, reg2,
    output [0:5]  Type,
    output [6:0]  Opcode,
    output [4:0] Rs1, Rs2, Rdt,
    output [31:0] Op1, Op2,
    output [19:0] Immediate */
    );
//////////////////////////////////////////////////////////////////////////////////
// DECLARATIONS

    //Fetch Unit declarations
    wire Branch;
    wire [9:0]  TargetAddress;
    wire [31:0] Instruction;
    wire [9:0]  instruction_address;
    
    wire ready_fetch; //Fetch handshake wire
    
    //Decode Unit declarations
    wire [0:5]  type;
    wire [9:0] current_address;
    wire [6:0]  opcode; 
    wire [3:0]  alu_opcode;
    wire [4:0]  rs1, rs2, rdt;
    wire [2:0]  funct3;
    wire [6:0]  funct7;
    wire [19:0] imm;
    
    wire ready_decode, ack_decode; //Decode handshake wires
    
    //Execute Unit declarations
    wire [31:0] op1, op2;
    wire [4:0] reg_address;
    wire [31:0] mem_address, store_data;
    wire [0:5]  type_out;
    wire valid;
    
    //Reference outputs
    //assign {Type, Opcode, Op1, Op2, Immediate} = {type_out, opcode, op1, op2, imm};
    
    wire ready_execute, ack_execute; //Execute handshake wires
    
    //Memory Writeback Unit declarations
    reg [31:0]  write_data;
    reg [4:0]   reg_file_address;
    reg [0:5]   type_reg;
    
    reg ack_writeback = 1; //Memory Writeback handshake wire
    
//////////////////////////////////////////////////////////////////////////////////
// FUNCTIONAL UNITS

    //Instruction RAM
    wire write_enable;
    wire [31:0] data_in;
    wire [31:0] data_out;
    reg [9:0] Ram_add;

    RAM i_ram(
    .write_enable(write_enable),
    .address(Ram_add),
    .data_in(data_in),
    .data_out(data_out)
    );
    
    //Data RAM
    wire [31:0] load_data;
    reg [9:0] read_mem_address, write_mem_address;
    reg store=0;
    
    Data_RAM data_ram(
    .write_enable(store),
    .read_address(read_mem_address),
    .write_address(write_mem_address),
    .data_in(store_data),
    .data_out(load_data)
    );
  
    //Register File
    reg [31:0] Reg_File [0:31];
    integer loop;
    initial begin
        for(loop=0; loop<32; loop=loop+1)
            Reg_File[loop] = 0;
    end
         
    assign op1 = Reg_File[rs1];
    assign op2 = type[0] ? Reg_File[rs2] : (type[1] ? load_data : 0);
    
    //Operand Forward Control
    always @ * begin
        if(Branch) 
            Ram_add = TargetAddress;
        else 
            Ram_add = instruction_address;
        
        read_mem_address = Reg_File[rs1] + imm;
    end
            
    
//////////////////////////////////////////////////////////////////////////////////
    //PIPELINE BEGINS
    
    Fetch fu(
    .enable(ack_decode),
    .Reset(Reset),
    .Branch(Branch),
    .TargetAddress(TargetAddress),
    .plus32(data_out),
    .ready_fetch(ready_fetch),
    .Instruction(Instruction),
    .Add(instruction_address)
    );
    
    Decode du(
    //.ready_fetch(ready_fetch),
    //.ack_execute(ack_execute),
    .enable(ready_fetch & ack_execute),
    .instruction(Instruction),
    .instr_add(instruction_address),
    
    .ack_decode(ack_decode),
    .ready_decode(ready_decode),
    .type(type),
    .address(current_address),
    .opcode(opcode), .alu_opcode(alu_opcode),
    .rs1(rs1), .rs2(rs2), .rdt(rdt),
    .funct3(funct3), .funct7(funct7),
    .imm(imm)
    );
    
    Execute eu(
    //.ready_decode(ready_decode),
    //.ack_writeback(ack_writeback),
    .enable(ready_decode & ack_writeback),
    .type_in(type), .rdt(rdt),
    .opcode_in(opcode), .alu_opcode_in(alu_opcode),
    .op1_in(op1), .op2_in(op2),
    .funct3_in(funct3), .funct7_in(funct7),
    .imm_in(imm), .address_in(current_address),
    
    .ack_execute(ack_execute),
    .ready_execute(ready_execute),
    .type_out(type_out),
    .branch(Branch),
    .reg_address(reg_address),
    .mem_address(mem_address), 
    .store_data(store_data),
    .targetAddress(TargetAddress),
    .valid(valid)
    );
        
//////////////////////////////////////////////////////////////////////////////////
    //  MEMORY ACCESS AND WRITE BACK LOGIC
    
    wire r, i, s, b, u, j; 
    assign {r, i, s, b, u, j} = type_reg;

    assign out = Instruction; //current_address;
    assign {reg0, reg1, reg2} = {Reg_File[0], Reg_File[2], Reg_File[4]};
    assign {Rs1, Rs2, Rdt} = {rs1, rs2, rdt};
        
    always @ (posedge (ready_execute & valid)) begin
            #1;
            ack_writeback = 0;
            type_reg = type_out;
            write_data = store_data;
            write_mem_address = mem_address;
            reg_file_address = reg_address;
            #2;
            //Writing to Register File / Store operation
            if(s) begin
                store = 1; 
                #1 store = 0;
            end
            else Reg_File[reg_file_address] = write_data;
            
            #1 ack_writeback = 1;
    end
    
endmodule