Branch.v

`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date: 05.02.2025 11:37:19
// Design Name: 
// Module Name: Branch
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
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module Branch(
    input enable, j, b,
    input [2:0] funct3,
    input [19:0] imm,
    input [31:0] op1, op2,
    input [9:0] address,
    
    output reg branch,
    output reg [9:0] targetAddress,
    output reg done
    );
    
    reg signed [31:0] s_op1, s_op2;
    
    always @ (posedge enable) begin
        done = 0;
            targetAddress = address + imm;
            s_op1 = op1; s_op2 = op2;
            #1;
            //Branch Logic
            if(j) branch = 1;
            else if(b) begin
                case(funct3)
                    3'b000: branch = (op1 == op2);
                    3'b001: branch = ~(op1 == op2);
                    3'b100: branch = (s_op1 < s_op2);
                    3'b101: branch = ~(s_op1 < s_op2);
                    3'b110: branch = (op1 < op2);
                    3'b111: branch = ~(op1 < op2);
                    default: branch = 0;
                endcase
            end
            else branch = 0;
            #1 done = 1;
    end
    
endmodule