Execute.v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 05.02.2025 11:38:05
// Design Name: 
// Module Name: Execute
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module Execute(
    input enable, //ready_decode, ack_writeback,
    input [0:5] type_in,
    input [4:0] rdt,
    input [3:0] alu_opcode_in,
    input [6:0] opcode_in,
    input [31:0] op1_in, op2_in,
    input [2:0] funct3_in,
    input [6:0] funct7_in,
    input [19:0] imm_in,
    input [9:0] address_in,
    
    output ack_execute, ready_execute,
    output [0:5] type_out,
    output reg branch,
    output reg [4:0] reg_address,
    output [31:0] mem_address,
    output reg [31:0] store_data,
    output [9:0] targetAddress,
    output reg valid
    );
        
    reg r, i, s, b, u, j;
    reg [3:0] alu_opcode;
    reg [6:0] opcode;
    reg [31:0] op1, op2;
    reg [2:0] funct3;
    reg [6:0] funct7;
    reg [19:0] imm;
    reg [9:0] address;
    
    wire [31:0] alu_result, lsu_out;
    wire take_branch;

    wire ready = 1;
    assign ready_execute = ready;
    assign ack_execute = ready;
    
    assign type_out = {r, i, s, b, u, j};
        
    //wire enable = ready_decode & ack_writeback;
    
    reg bu_en, alu_en, lsu_en;
    wire alu_done, lsu_done, bu_done;
    wire complete;

    wire alu_check = alu_done && alu_en;
    wire lsu_check = lsu_done && lsu_en;
    wire bu_check = bu_done && bu_en;
    
    assign ready = alu_check | lsu_check | bu_check;
    
    always @ (posedge enable) begin
            #1;
            {bu_en, alu_en, lsu_en} = 3'b000;
            valid = |type_in;
            #1;
            if(valid) begin 
                //Importing Pipeline Data
                {r, i, s, b, u, j} = type_in;
                opcode = opcode_in;
                op1 = op1_in; op2 = op2_in;
                alu_opcode = alu_opcode_in;
                funct3 = funct3_in;
                funct7 = funct7_in;
                imm = imm_in;
                address = address_in;
                reg_address = rdt;
                 
                #1;
                
                //Deciding on Branch Unit, ALU or LSU        
                if(r){bu_en, alu_en, lsu_en} = 3'b010;
                else if(s | u) {bu_en, alu_en, lsu_en} = 3'b001;
                else if(b | j) {bu_en, alu_en, lsu_en} = 3'b100;
                else if(i) begin
                    if(opcode==7'h00000013) {bu_en, alu_en, lsu_en} = 3'b010;
                    else {bu_en, alu_en, lsu_en} = 3'b001;
                end
                else {bu_en, alu_en, lsu_en} = 3'b000;

            end
    end

    always @ (posedge alu_check or posedge lsu_check) begin
            #1; //Obtaining appropriate output value
            if(alu_check) store_data = alu_result;
            else if(lsu_check) store_data = lsu_out;
    end
    
    //Deciding on Branch status
    always @ (posedge ready) branch = bu_check ? take_branch : 1'b0;
    
    //Execute Unit Sub-module Istantiations
    Branch bu(
    .enable(bu_en),
    .j(j), .b(b),
    .funct3(funct3), .imm(imm),
    .op1(op1), .op2(op2),
    .address(address),
    .branch(take_branch),
    .targetAddress(targetAddress),
    .done(bu_done)
    );
    
    ALU alu(
    .enable(alu_en),
    .r(r), .i(i),
    .op1(op1), .op2(op2),
    .imm(imm), 
    .opcode(opcode),
    .alu_opcode(alu_opcode),
    .result(alu_result),
    .done(alu_done)
    );
    
    Loadstore lsu(
    .enable(lsu_en),
    .s(s), .u(u),
    .funct3(funct3), 
    .imm(imm), 
    .op1(op1), .op2(op2), 
    .mem_address(mem_address), 
    .store_data(lsu_out),
    .done(lsu_done)
    );

endmodule