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VyacheslavLevytskyyVyacheslavLevytskyy
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[SPIR-V] Implement support of the SPV_EXT_arithmetic_fence SPIRV extension (llvm#110500)
This PR implements support of the SPV_EXT_arithmetic_fence SPIRV extension: https://htmlpreview.github.io/?https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/EXT/SPV_EXT_arithmetic_fence.html.
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‎llvm/docs/SPIRVUsage.rst‎

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@@ -147,6 +147,8 @@ list of supported SPIR-V extensions, sorted alphabetically by their extension na
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- Adds atomic add instruction on floating-point numbers.
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* - ``SPV_EXT_shader_atomic_float_min_max``
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- Adds atomic min and max instruction on floating-point numbers.
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* - ``SPV_EXT_arithmetic_fence``
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- Adds an instruction that prevents fast-math optimizations between its argument and the expression that contains it.
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* - ``SPV_INTEL_arbitrary_precision_integers``
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- Allows generating arbitrary width integer types.
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* - ``SPV_INTEL_bfloat16_conversion``

‎llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp‎

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@@ -28,6 +28,8 @@ static const std::map<std::string, SPIRV::Extension::Extension>
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SPIRV::Extension::Extension::SPV_EXT_shader_atomic_float16_add},
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{"SPV_EXT_shader_atomic_float_min_max",
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SPIRV::Extension::Extension::SPV_EXT_shader_atomic_float_min_max},
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{"SPV_EXT_arithmetic_fence",
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SPIRV::Extension::Extension::SPV_EXT_arithmetic_fence},
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{"SPV_INTEL_arbitrary_precision_integers",
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SPIRV::Extension::Extension::SPV_INTEL_arbitrary_precision_integers},
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{"SPV_INTEL_cache_controls",

‎llvm/lib/Target/SPIRV/SPIRVInstrInfo.td‎

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@@ -878,3 +878,7 @@ def OpCooperativeMatrixMulAddKHR: Op<4459, (outs ID:$res),
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"$res = OpCooperativeMatrixMulAddKHR $type $A $B $C">;
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def OpCooperativeMatrixLengthKHR: Op<4460, (outs ID:$res), (ins TYPE:$type, ID:$coop_matr_type),
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"$res = OpCooperativeMatrixLengthKHR $type $coop_matr_type">;
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// SPV_EXT_arithmetic_fence
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def OpArithmeticFenceEXT: Op<6145, (outs ID:$res), (ins TYPE:$type, ID:$target),
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"$res = OpArithmeticFenceEXT $type $target">;

‎llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp‎

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@@ -2600,6 +2600,16 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
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.addUse(I.getOperand(2).getReg())
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.addUse(I.getOperand(3).getReg());
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break;
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case Intrinsic::arithmetic_fence:
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if (STI.canUseExtension(SPIRV::Extension::SPV_EXT_arithmetic_fence))
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BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpArithmeticFenceEXT))
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.addDef(ResVReg)
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.addUse(GR.getSPIRVTypeID(ResType))
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.addUse(I.getOperand(2).getReg());
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else
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BuildMI(BB, I, I.getDebugLoc(), TII.get(TargetOpcode::COPY), ResVReg)
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.addUse(I.getOperand(2).getReg());
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break;
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case Intrinsic::spv_thread_id:
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return selectSpvThreadId(ResVReg, ResType, I);
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case Intrinsic::spv_fdot:

‎llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp‎

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@@ -1200,6 +1200,14 @@ void addInstrRequirements(const MachineInstr &MI,
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Reqs.addExtension(SPIRV::Extension::SPV_KHR_cooperative_matrix);
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Reqs.addCapability(SPIRV::Capability::CooperativeMatrixKHR);
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break;
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case SPIRV::OpArithmeticFenceEXT:
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if (!ST.canUseExtension(SPIRV::Extension::SPV_EXT_arithmetic_fence))
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report_fatal_error("OpArithmeticFenceEXT requires the "
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"following SPIR-V extension: SPV_EXT_arithmetic_fence",
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false);
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Reqs.addExtension(SPIRV::Extension::SPV_EXT_arithmetic_fence);
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Reqs.addCapability(SPIRV::Capability::ArithmeticFenceEXT);
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break;
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default:
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break;
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}

‎llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td‎

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@@ -303,6 +303,7 @@ defm SPV_INTEL_cache_controls : ExtensionOperand<108>;
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defm SPV_INTEL_global_variable_host_access : ExtensionOperand<109>;
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defm SPV_INTEL_global_variable_fpga_decorations : ExtensionOperand<110>;
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defm SPV_KHR_cooperative_matrix : ExtensionOperand<111>;
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defm SPV_EXT_arithmetic_fence : ExtensionOperand<112>;
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//===----------------------------------------------------------------------===//
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// Multiclass used to define Capabilities enum values and at the same time
@@ -480,6 +481,7 @@ defm HostAccessINTEL : CapabilityOperand<6188, 0, 0, [SPV_INTEL_global_variable_
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defm GlobalVariableFPGADecorationsINTEL : CapabilityOperand<6189, 0, 0, [SPV_INTEL_global_variable_fpga_decorations], []>;
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defm CacheControlsINTEL : CapabilityOperand<6441, 0, 0, [SPV_INTEL_cache_controls], []>;
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defm CooperativeMatrixKHR : CapabilityOperand<6022, 0, 0, [SPV_KHR_cooperative_matrix], []>;
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defm ArithmeticFenceEXT : CapabilityOperand<6144, 0, 0, [SPV_EXT_arithmetic_fence], []>;
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//===----------------------------------------------------------------------===//
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// Multiclass used to define SourceLanguage enum values and at the same time

‎llvm/test/CodeGen/SPIRV/llvm-intrinsics/arithmetic-fence.ll‎

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; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-linux %s -o - | FileCheck %s --check-prefixes=CHECK-NOEXT
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; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
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; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-linux %s -o - --spirv-ext=+SPV_EXT_arithmetic_fence | FileCheck %s --check-prefixes=CHECK-EXT
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; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
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; CHECK-NOEXT-NO: OpCapability ArithmeticFenceEXT
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; CHECK-NOEXT-NO: OpExtension "SPV_EXT_arithmetic_fence"
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; CHECK-NOEXT: OpFunction
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; CHECK-NOEXT: OpFMul
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; CHECK-NOEXT: OpFAdd
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; CHECK-NOEXT-NO: OpArithmeticFenceEXT
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; CHECK-NOEXT: OpFunction
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; CHECK-NOEXT-NO: OpArithmeticFenceEXT
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; CHECK-NOEXT: OpFunction
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; CHECK-NOEXT-NO: OpArithmeticFenceEXT
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; CHECK-EXT: OpCapability ArithmeticFenceEXT
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; CHECK-EXT: OpExtension "SPV_EXT_arithmetic_fence"
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; CHECK-EXT: OpFunction
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; CHECK-EXT: [[R1:%.*]] = OpFMul [[I32Ty:%.*]] %[[#]] %[[#]]
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; CHECK-EXT: [[R2:%.*]] = OpArithmeticFenceEXT [[I32Ty]] [[R1]]
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; CHECK-EXT: %[[#]] = OpFAdd [[I32Ty]] [[R2]] %[[#]]
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; CHECK-EXT: OpFunction
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; CHECK-EXT: [[R3:%.*]] = OpFAdd [[I64Ty:%.*]] [[A1:%.*]] [[A1]]
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; CHECK-EXT: [[R4:%.*]] = OpArithmeticFenceEXT [[I64Ty]] [[R3]]
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; CHECK-EXT: [[R5:%.*]] = OpFAdd [[I64Ty]] [[A1]] [[A1]]
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; CHECK-EXT: %[[#]] = OpFAdd [[I64Ty]] [[R4]] [[R5]]
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; CHECK-EXT: OpFunction
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; CHECK-EXT: [[R6:%.*]] = OpFAdd [[I32VecTy:%.*]] [[A2:%.*]] [[A2]]
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; CHECK-EXT: [[R7:%.*]] = OpArithmeticFenceEXT [[I32VecTy]] [[R6]]
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; CHECK-EXT: [[R8:%.*]] = OpFAdd [[I32VecTy]] [[A2]] [[A2]]
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; CHECK-EXT: %[[#]] = OpFAdd [[I32VecTy]] [[R7]] [[R8]]
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define float @f1(float %a, float %b, float %c) {
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%mul = fmul fast float %b, %a
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%tmp = call float @llvm.arithmetic.fence.f32(float %mul)
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%add = fadd fast float %tmp, %c
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ret float %add
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}
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define double @f2(double %a) {
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%1 = fadd fast double %a, %a
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%t = call double @llvm.arithmetic.fence.f64(double %1)
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%2 = fadd fast double %a, %a
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%3 = fadd fast double %t, %2
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ret double %3
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}
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define <2 x float> @f3(<2 x float> %a) {
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%1 = fadd fast <2 x float> %a, %a
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%t = call <2 x float> @llvm.arithmetic.fence.v2f32(<2 x float> %1)
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%2 = fadd fast <2 x float> %a, %a
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%3 = fadd fast <2 x float> %t, %2
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ret <2 x float> %3
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}
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declare float @llvm.arithmetic.fence.f32(float)
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declare double @llvm.arithmetic.fence.f64(double)
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declare <2 x float> @llvm.arithmetic.fence.v2f32(<2 x float>)

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