@@ -68,6 +68,14 @@ def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", []>, TB;
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def SYSEXIT : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", []>, TB;
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def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexitq", []>, TB,
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Requires<[In64BitMode]>;
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+
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+ // FRED Instructions
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+ let hasSideEffects = 1, Defs = [RSP, EFLAGS] in {
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+ def ERETS: I<0x01, MRM_CA, (outs), (ins), "erets",
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+ []>, TB, XD, Requires<[In64BitMode]>;
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+ def ERETU: I<0x01, MRM_CA, (outs), (ins), "eretu",
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+ []>, TB, XS, Requires<[In64BitMode]>;
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+ } // hasSideEffects = 1, Defs = [RSP, EFLAGS]
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} // SchedRW
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def : Pat<(debugtrap),
@@ -212,6 +220,14 @@ def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
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let SchedRW = [WriteSystem] in {
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def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", []>, TB;
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+ // LKGS instructions
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+ let hasSideEffects = 1 in {
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+ let mayLoad = 1 in
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+ def LKGS16m : I<0x00, MRM6m, (outs), (ins i16mem:$src), "lkgs\t$src",
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+ []>, TB, XD, Requires<[In64BitMode]>;
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+ def LKGS16r : I<0x00, MRM6r, (outs), (ins GR16:$src), "lkgs\t$src",
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+ []>, TB, XD, Requires<[In64BitMode]>;
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+ } // hasSideEffects
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let Defs = [EFLAGS] in {
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let mayLoad = 1 in
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