@@ -4183,37 +4183,37 @@ X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
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{ ISD::FSQRT, MVT::v4f32, { 56 , 56 , 1 , 2 } }, // Pentium III from http://www.agner.org/
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};
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static const CostKindTblEntry BMI64CostTbl[] = { // 64-bit targets
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- { ISD::CTTZ, MVT::i64 , { 1 } },
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+ { ISD::CTTZ, MVT::i64 , { 1 , 1 , 1 , 1 } },
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};
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static const CostKindTblEntry BMI32CostTbl[] = { // 32 or 64-bit targets
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- { ISD::CTTZ, MVT::i32 , { 1 } },
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- { ISD::CTTZ, MVT::i16 , { 1 } },
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- { ISD::CTTZ, MVT::i8 , { 1 } },
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+ { ISD::CTTZ, MVT::i32 , { 1 , 1 , 1 , 1 } },
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+ { ISD::CTTZ, MVT::i16 , { 2 , 1 , 1 , 1 } },
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+ { ISD::CTTZ, MVT::i8 , { 2 , 1 , 1 , 1 } },
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};
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static const CostKindTblEntry LZCNT64CostTbl[] = { // 64-bit targets
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- { ISD::CTLZ, MVT::i64 , { 1 } },
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+ { ISD::CTLZ, MVT::i64 , { 1 , 1 , 1 , 1 } },
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};
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static const CostKindTblEntry LZCNT32CostTbl[] = { // 32 or 64-bit targets
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- { ISD::CTLZ, MVT::i32 , { 1 } },
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- { ISD::CTLZ, MVT::i16 , { 2 } },
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- { ISD::CTLZ, MVT::i8 , { 2 } },
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+ { ISD::CTLZ, MVT::i32 , { 1 , 1 , 1 , 1 } },
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+ { ISD::CTLZ, MVT::i16 , { 2 , 1 , 1 , 1 } },
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+ { ISD::CTLZ, MVT::i8 , { 2 , 1 , 1 , 1 } },
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};
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static const CostKindTblEntry POPCNT64CostTbl[] = { // 64-bit targets
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- { ISD::CTPOP, MVT::i64 , { 1 , 1 , 1 , 1 } }, // popcnt
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+ { ISD::CTPOP, MVT::i64 , { 1 , 1 , 1 , 1 } }, // popcnt
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};
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static const CostKindTblEntry POPCNT32CostTbl[] = { // 32 or 64-bit targets
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- { ISD::CTPOP, MVT::i32 , { 1 , 1 , 1 , 1 } }, // popcnt
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- { ISD::CTPOP, MVT::i16 , { 1 , 1 , 2 , 2 } }, // popcnt(zext())
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- { ISD::CTPOP, MVT::i8 , { 1 , 1 , 2 , 2 } }, // popcnt(zext())
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+ { ISD::CTPOP, MVT::i32 , { 1 , 1 , 1 , 1 } }, // popcnt
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+ { ISD::CTPOP, MVT::i16 , { 1 , 1 , 2 , 2 } }, // popcnt(zext())
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+ { ISD::CTPOP, MVT::i8 , { 1 , 1 , 2 , 2 } }, // popcnt(zext())
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};
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static const CostKindTblEntry X64CostTbl[] = { // 64-bit targets
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{ ISD::ABS, MVT::i64 , { 1 , 2 , 3 , 3 } }, // SUB+CMOV
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{ ISD::BITREVERSE, MVT::i64 , { 10 , 12 , 20 , 22 } },
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{ ISD::BSWAP, MVT::i64 , { 1 , 2 , 1 , 2 } },
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- { ISD::CTLZ, MVT::i64 , { 4 } }, // BSR+XOR or BSR+XOR+CMOV
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- { ISD::CTLZ_ZERO_UNDEF, MVT::i64 ,{ 1 , 1 , 1 , 1 } }, // BSR+XOR
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- { ISD::CTTZ, MVT::i64 , { 3 } }, // TEST+BSF+CMOV/BRANCH
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- { ISD::CTTZ_ZERO_UNDEF, MVT::i64 ,{ 1 , 1 , 1 , 1 } }, // BSR
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+ { ISD::CTLZ, MVT::i64 , { 3 , 2 , 6 , 6 } }, // BSR+XOR or BSR+XOR+CMOV
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+ { ISD::CTLZ_ZERO_UNDEF, MVT::i64 ,{ 1 , 2 , 2 , 2 } }, // BSR+XOR
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+ { ISD::CTTZ, MVT::i64 , { 2 , 2 , 5 , 5 } }, // TEST+BSF+CMOV/BRANCH
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+ { ISD::CTTZ_ZERO_UNDEF, MVT::i64 ,{ 1 , 2 , 1 , 2 } }, // BSF
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{ ISD::CTPOP, MVT::i64 , { 10 , 6 , 19 , 19 } },
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{ ISD::ROTL, MVT::i64 , { 2 , 3 , 1 , 3 } },
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{ ISD::ROTR, MVT::i64 , { 2 , 3 , 1 , 3 } },
@@ -4241,18 +4241,18 @@ X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
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{ ISD::BITREVERSE, MVT::i8 , { 7 , 9 , 13 , 14 } },
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{ ISD::BSWAP, MVT::i32 , { 1 , 1 , 1 , 1 } },
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{ ISD::BSWAP, MVT::i16 , { 1 , 2 , 1 , 2 } }, // ROL
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- { ISD::CTLZ, MVT::i32 , { 4 } }, // BSR+XOR or BSR+XOR+CMOV
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- { ISD::CTLZ, MVT::i16 , { 4 } }, // BSR+XOR or BSR+XOR+CMOV
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- { ISD::CTLZ, MVT::i8 , { 4 } }, // BSR+XOR or BSR+XOR+CMOV
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- { ISD::CTLZ_ZERO_UNDEF, MVT::i32 ,{ 1 , 1 , 1 , 1 } }, // BSR+XOR
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- { ISD::CTLZ_ZERO_UNDEF, MVT::i16 ,{ 2 , 2 , 3 , 3 } }, // BSR+XOR
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+ { ISD::CTLZ, MVT::i32 , { 3 , 2 , 6 , 6 } }, // BSR+XOR or BSR+XOR+CMOV
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+ { ISD::CTLZ, MVT::i16 , { 3 , 2 , 6 , 6 } }, // BSR+XOR or BSR+XOR+CMOV
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+ { ISD::CTLZ, MVT::i8 , { 3 , 2 , 7 , 7 } }, // BSR+XOR or BSR+XOR+CMOV
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+ { ISD::CTLZ_ZERO_UNDEF, MVT::i32 ,{ 1 , 2 , 2 , 2 } }, // BSR+XOR
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+ { ISD::CTLZ_ZERO_UNDEF, MVT::i16 ,{ 2 , 2 , 2 , 2 } }, // BSR+XOR
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{ ISD::CTLZ_ZERO_UNDEF, MVT::i8 , { 2 , 2 , 3 , 3 } }, // BSR+XOR
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- { ISD::CTTZ, MVT::i32 , { 3 } }, // TEST+BSF+CMOV/BRANCH
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- { ISD::CTTZ, MVT::i16 , { 3 } }, // TEST+BSF+CMOV/BRANCH
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- { ISD::CTTZ, MVT::i8 , { 3 } }, // TEST+BSF+CMOV/BRANCH
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- { ISD::CTTZ_ZERO_UNDEF, MVT::i32 ,{ 1 , 1 , 1 , 1 } }, // BSF
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- { ISD::CTTZ_ZERO_UNDEF, MVT::i16 ,{ 2 , 2 , 1 , 1 } }, // BSF
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- { ISD::CTTZ_ZERO_UNDEF, MVT::i8 , { 2 , 2 , 1 , 1 } }, // BSF
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+ { ISD::CTTZ, MVT::i32 , { 2 , 2 , 3 , 3 } }, // TEST+BSF+CMOV/BRANCH
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+ { ISD::CTTZ, MVT::i16 , { 2 , 2 , 2 , 3 } }, // TEST+BSF+CMOV/BRANCH
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+ { ISD::CTTZ, MVT::i8 , { 2 , 2 , 2 , 3 } }, // TEST+BSF+CMOV/BRANCH
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+ { ISD::CTTZ_ZERO_UNDEF, MVT::i32 ,{ 1 , 2 , 1 , 2 } }, // BSF
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+ { ISD::CTTZ_ZERO_UNDEF, MVT::i16 ,{ 2 , 2 , 1 , 2 } }, // BSF
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+ { ISD::CTTZ_ZERO_UNDEF, MVT::i8 , { 2 , 2 , 1 , 2 } }, // BSF
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{ ISD::CTPOP, MVT::i32 , { 8 , 7 , 15 , 15 } },
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{ ISD::CTPOP, MVT::i16 , { 9 , 8 , 17 , 17 } },
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{ ISD::CTPOP, MVT::i8 , { 7 , 6 , 6 , 6 } },
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