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[AMDGPU] Add support for v_cvt_pk_f16_fp8 on gfx1250 (llvm#145747)
Co-authored-by: Shilei Tian <[email protected]>
1 parent 6fd182a commit ff23ee4

25 files changed

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lines changed

‎clang/include/clang/Basic/BuiltinsAMDGPU.def‎

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@@ -642,5 +642,7 @@ TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_f16_f32, "V2hV2hfUiIb", "nc", "f32-to-f16
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TARGET_BUILTIN(__builtin_amdgcn_s_setprio_inc_wg, "vIs", "n", "setprio-inc-wg-inst")
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TARGET_BUILTIN(__builtin_amdgcn_cvt_pk_f16_fp8, "V2hs", "nc", "gfx1250-insts")
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#undef BUILTIN
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#undef TARGET_BUILTIN

‎clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl‎

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@@ -10,3 +10,23 @@
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void test_setprio_inc_wg() {
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__builtin_amdgcn_s_setprio_inc_wg(10);
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}
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// CHECK-LABEL: @test_cvt_pk_f16_fp8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[OUT_ADDR:%.*]] = alloca ptr addrspace(1), align 8, addrspace(5)
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2, addrspace(5)
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// CHECK-NEXT: [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT_ADDR]] to ptr
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// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr
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// CHECK-NEXT: store ptr addrspace(1) [[OUT:%.*]], ptr [[OUT_ADDR_ASCAST]], align 8
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// CHECK-NEXT: store i16 [[A:%.*]], ptr [[A_ADDR_ASCAST]], align 2
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// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A_ADDR_ASCAST]], align 2
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// CHECK-NEXT: [[TMP1:%.*]] = call <2 x half> @llvm.amdgcn.cvt.pk.f16.fp8(i16 [[TMP0]])
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// CHECK-NEXT: [[TMP2:%.*]] = load ptr addrspace(1), ptr [[OUT_ADDR_ASCAST]], align 8
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// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds <2 x half>, ptr addrspace(1) [[TMP2]], i64 0
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// CHECK-NEXT: store <2 x half> [[TMP1]], ptr addrspace(1) [[ARRAYIDX]], align 4
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// CHECK-NEXT: ret void
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//
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void test_cvt_pk_f16_fp8(global half2* out, short a)
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{
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out[0] = __builtin_amdgcn_cvt_pk_f16_fp8(a);
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}

‎llvm/include/llvm/IR/IntrinsicsAMDGPU.td‎

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@@ -588,6 +588,10 @@ def int_amdgcn_ds_ordered_swap : AMDGPUDSOrderedIntrinsic;
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def int_amdgcn_ds_append : AMDGPUDSAppendConsumedIntrinsic;
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def int_amdgcn_ds_consume : AMDGPUDSAppendConsumedIntrinsic;
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def int_amdgcn_cvt_pk_f16_fp8 : DefaultAttrsIntrinsic<
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[llvm_v2f16_ty], [llvm_i16_ty], [IntrNoMem, IntrSpeculatable]
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>, ClangBuiltin<"__builtin_amdgcn_cvt_pk_f16_fp8">;
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class AMDGPUCvtScaleF32Intrinsic<LLVMType DstTy, LLVMType Src0Ty, string name> : DefaultAttrsIntrinsic<
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[DstTy], [Src0Ty, llvm_float_ty], [IntrNoMem, IntrSpeculatable]
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>, ClangBuiltin<"__builtin_amdgcn_"#name>;

‎llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp‎

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@@ -4541,6 +4541,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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case Intrinsic::amdgcn_cvt_pknorm_u16:
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case Intrinsic::amdgcn_cvt_pk_i16:
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case Intrinsic::amdgcn_cvt_pk_u16:
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case Intrinsic::amdgcn_cvt_pk_f16_fp8:
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case Intrinsic::amdgcn_fmed3:
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case Intrinsic::amdgcn_cubeid:
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case Intrinsic::amdgcn_cubema:

‎llvm/lib/Target/AMDGPU/VOP1Instructions.td‎

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@@ -729,6 +729,21 @@ let SubtargetPredicate = isGFX12Plus, OtherPredicates = [HasFP8ConversionInsts]
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}
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}
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// FIXME-TRUE16: True16 versions of these instructions are untested.
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let HasExtSDWA = 0, HasOpSel = 1, EmitDstSel = 0, HasOMod = 0, HasModifiers = 1 in {
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def VOPProfile_CVT_PK_F16_F8 : VOPProfile<[v2f16, i16, untyped, untyped]>;
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def VOPProfile_CVT_PK_F16_F8_true16 : VOP3_Profile_True16<VOPProfile_CVT_PK_F16_F8>;
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def VOPProfile_CVT_PK_F16_F8_fake16 : VOP3_Profile_Fake16<VOPProfile_CVT_PK_F16_F8>;
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}
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let SubtargetPredicate = isGFX1250Plus in {
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let mayRaiseFPException = 0, SchedRW = [WriteFloatCvt] in {
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defm V_CVT_PK_F16_FP8 : VOP1Inst_t16_with_profiles<"v_cvt_pk_f16_fp8",
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VOPProfile_CVT_PK_F16_F8, VOPProfile_CVT_PK_F16_F8_true16, VOPProfile_CVT_PK_F16_F8_fake16,
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int_amdgcn_cvt_pk_f16_fp8>;
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}
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} // End SubtargetPredicate = isGFX1250Plus
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let SubtargetPredicate = isGFX10Plus in {
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defm V_PIPEFLUSH : VOP1Inst<"v_pipeflush", VOP_NO_EXT<VOP_NONE>>;
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@@ -1062,6 +1077,7 @@ defm V_CVT_F16_F32 : VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<0x00a>;
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defm V_CVT_F32_F16 : VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<0x00b>;
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defm V_CVT_F32_BF16 : VOP1_Real_FULL_t16_and_fake16_gfx1250<0x072, "v_cvt_f32_bf16", "V_CVT_F32_BF16_gfx1250">;
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defm V_CVT_PK_F16_FP8 : VOP1_Real_FULL_t16_and_fake16_gfx1250<0x075>;
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//===----------------------------------------------------------------------===//
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// GFX10.

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll‎

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@@ -0,0 +1,72 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 %s -o - | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG-REAL16 %s
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 %s -o - | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG-FAKE16 %s
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; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 %s -o - | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL-REAL16 %s
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; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 %s -o - | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL-FAKE16 %s
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define amdgpu_ps float @test_cvt_pk_f16_fp8_v(i16 %a) {
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; GFX1250-SDAG-REAL16-LABEL: test_cvt_pk_f16_fp8_v:
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; GFX1250-SDAG-REAL16: ; %bb.0:
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; GFX1250-SDAG-REAL16-NEXT: v_cvt_pk_f16_fp8 v0, v0.l
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; GFX1250-SDAG-REAL16-NEXT: ; return to shader part epilog
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;
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; GFX1250-SDAG-FAKE16-LABEL: test_cvt_pk_f16_fp8_v:
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; GFX1250-SDAG-FAKE16: ; %bb.0:
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; GFX1250-SDAG-FAKE16-NEXT: v_cvt_pk_f16_fp8 v0, v0
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; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog
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;
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; GFX1250-GISEL-REAL16-LABEL: test_cvt_pk_f16_fp8_v:
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; GFX1250-GISEL-REAL16: ; %bb.0:
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; GFX1250-GISEL-REAL16-NEXT: v_cvt_pk_f16_fp8 v0, v0.l
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; GFX1250-GISEL-REAL16-NEXT: ; return to shader part epilog
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;
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; GFX1250-GISEL-FAKE16-LABEL: test_cvt_pk_f16_fp8_v:
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; GFX1250-GISEL-FAKE16: ; %bb.0:
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; GFX1250-GISEL-FAKE16-NEXT: v_cvt_pk_f16_fp8 v0, v0
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; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog
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%cvt = tail call <2 x half> @llvm.amdgcn.cvt.pk.f16.fp8(i16 %a)
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%ret = bitcast <2 x half> %cvt to float
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ret float %ret
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}
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define amdgpu_ps float @test_cvt_pk_f16_fp8_s(i16 inreg %a) {
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; GFX1250-LABEL: test_cvt_pk_f16_fp8_s:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: v_cvt_pk_f16_fp8 v0, s0
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; GFX1250-NEXT: ; return to shader part epilog
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%cvt = tail call <2 x half> @llvm.amdgcn.cvt.pk.f16.fp8(i16 %a)
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%ret = bitcast <2 x half> %cvt to float
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ret float %ret
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}
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define amdgpu_ps float @test_cvt_pk_f16_fp8_v_hi(<2 x i16> %a) {
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; GFX1250-SDAG-REAL16-LABEL: test_cvt_pk_f16_fp8_v_hi:
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; GFX1250-SDAG-REAL16: ; %bb.0:
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; GFX1250-SDAG-REAL16-NEXT: v_cvt_pk_f16_fp8 v0, v0.h
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; GFX1250-SDAG-REAL16-NEXT: ; return to shader part epilog
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;
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; GFX1250-SDAG-FAKE16-LABEL: test_cvt_pk_f16_fp8_v_hi:
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; GFX1250-SDAG-FAKE16: ; %bb.0:
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; GFX1250-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
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; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX1250-SDAG-FAKE16-NEXT: v_cvt_pk_f16_fp8 v0, v0
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; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog
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;
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; GFX1250-GISEL-REAL16-LABEL: test_cvt_pk_f16_fp8_v_hi:
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; GFX1250-GISEL-REAL16: ; %bb.0:
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; GFX1250-GISEL-REAL16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
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; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX1250-GISEL-REAL16-NEXT: v_cvt_pk_f16_fp8 v0, v0.l
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; GFX1250-GISEL-REAL16-NEXT: ; return to shader part epilog
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;
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; GFX1250-GISEL-FAKE16-LABEL: test_cvt_pk_f16_fp8_v_hi:
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; GFX1250-GISEL-FAKE16: ; %bb.0:
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; GFX1250-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
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; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX1250-GISEL-FAKE16-NEXT: v_cvt_pk_f16_fp8 v0, v0
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; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog
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%a.1 = extractelement <2 x i16> %a, i32 1
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%cvt = tail call <2 x half> @llvm.amdgcn.cvt.pk.f16.fp8(i16 %a.1)
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%ret = bitcast <2 x half> %cvt to float
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ret float %ret
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}

‎llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s‎

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@@ -45,3 +45,12 @@ v_cvt_f32_bf16 v5, src_scc
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v_cvt_f32_bf16 v127, 0x8000
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// GFX1250: v_cvt_f32_bf16_e32 v127, 0x8000 ; encoding: [0xff,0xe4,0xfe,0x7e,0x00,0x80,0x00,0x00]
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v_cvt_pk_f16_fp8 v1, v2
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// GFX1250: v_cvt_pk_f16_fp8 v1, v2 ; encoding: [0x02,0xeb,0x02,0x7e]
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v_cvt_pk_f16_fp8 v1, s2
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// GFX1250: v_cvt_pk_f16_fp8 v1, s2 ; encoding: [0x02,0xea,0x02,0x7e]
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v_cvt_pk_f16_fp8 v1, 100
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// GFX1250: v_cvt_pk_f16_fp8 v1, 0x64 ; encoding: [0xff,0xea,0x02,0x7e,0x64,0x00,0x00,0x00]

‎llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s‎

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@@ -48,3 +48,12 @@ v_cvt_f32_bf16 v127, 0x8000
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v_cvt_f32_bf16 v5, v1.h
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// GFX1250: v_cvt_f32_bf16_e32 v5, v1.h ; encoding: [0x81,0xe5,0x0a,0x7e]
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v_cvt_pk_f16_fp8 v1, v2
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// GFX1250: v_cvt_pk_f16_fp8 v1, v2 ; encoding: [0x02,0xeb,0x02,0x7e]
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v_cvt_pk_f16_fp8 v1, s2
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// GFX1250: v_cvt_pk_f16_fp8 v1, s2 ; encoding: [0x02,0xea,0x02,0x7e]
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v_cvt_pk_f16_fp8 v1, 100
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// GFX1250: v_cvt_pk_f16_fp8 v1, 0x64 ; encoding: [0xff,0xea,0x02,0x7e,0x64,0x00,0x00,0x00]

‎llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16-fake16.s‎

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@@ -57,3 +57,7 @@ v_cvt_f32_bf16 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
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v_cvt_f32_bf16 v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
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// GFX1250: v_cvt_f32_bf16_dpp v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xe4,0xfe,0x7e,0x7f,0x6f,0x35,0x30]
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// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
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v_cvt_pk_f16_fp8 v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf fi:1
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// GFX1250: v_cvt_pk_f16_fp8_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf fi:1 ; encoding: [0xfa,0xea,0x02,0x7e,0x02,0xe4,0x04,0xff]
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// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU

‎llvm/test/MC/AMDGPU/gfx1250_asm_vop1_dpp16.s‎

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@@ -61,3 +61,11 @@ v_cvt_f32_bf16 v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:
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v_cvt_f32_bf16 v5, v1.h quad_perm:[3,2,1,0]
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// GFX1250: v_cvt_f32_bf16_dpp v5, v1.h quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xe4,0x0a,0x7e,0x81,0x1b,0x00,0xff]
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// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
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v_cvt_pk_f16_fp8 v1, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf fi:1
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// GFX1250: v_cvt_pk_f16_fp8_dpp v1, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf fi:1 ; encoding: [0xfa,0xea,0x02,0x7e,0x02,0xe4,0x04,0xff]
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// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
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v_cvt_pk_f16_fp8 v1, v2.h quad_perm:[0,1,2,3]
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// GFX1250: v_cvt_pk_f16_fp8_dpp v1, v2.h quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xea,0x02,0x7e,0x82,0xe4,0x00,0xff]
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// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU

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