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Release v1.16.1
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‎Drivers/BSP/Components/otm8009a/Release_Notes.html‎

Lines changed: 249 additions & 223 deletions
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‎Drivers/BSP/Components/otm8009a/otm8009a.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -152,7 +152,7 @@ const uint8_t ShortRegData47[] = {0xC5, 0x66};
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const uint8_t ShortRegData48[] = {OTM8009A_CMD_NOP, 0xB6};
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const uint8_t ShortRegData49[] = {0xF5, 0x06};
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const uint8_t ShortRegData50[] = {OTM8009A_CMD_NOP, 0xB1};
155-
const uint8_t ShortRegData51[] = {0xC6, 0x06};
155+
const uint8_t ShortRegData51[] = {0xC6, 0x05};
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/**
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* @}
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*/
@@ -353,7 +353,7 @@ uint8_t OTM8009A_Init(uint32_t ColorCoding, uint32_t orientation)
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DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData49);
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/////////////////////////////////////////////////////////////////////////////
355355

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/* CABC LEDPWM frequency adjusted to 19,5kHz */
356+
/* CABC LEDPWM frequency adjusted to 22,7kHz */
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DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData50);
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DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData51);
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‎Drivers/BSP/Components/otm8009a/otm8009a.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -61,12 +61,12 @@
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* @{
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*/
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#if defined ( __GNUC__ )
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#if defined ( __GNUC__ ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) /* GNU and ARM Compiler 6 compilers */
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#ifndef __weak
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#define __weak __attribute__((weak))
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#endif /* __weak */
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#endif /* __GNUC__ */
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#endif /* __GNUC__ || (__ARMCC_VERSION && (__ARMCC_VERSION >= 6010050)) */
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/**
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* @brief LCD_OrientationTypeDef
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* Possible values of Display Orientation

‎Drivers/BSP/STM32746G-Discovery/License.md‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,3 @@
1+
# Copyright (c) *2015* STMicroelectronics
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This software component is licensed by STMicroelectronics under the **BSD-3-Clause** license. You may not use this software except in compliance with this license. You may obtain a copy of the license [here](https://opensource.org/licenses/BSD-3-Clause).

‎Drivers/BSP/STM32746G-Discovery/Release_Notes.html‎

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<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">&nbsp;&nbsp;&nbsp; Update History</span></h2>
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<span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span>
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<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.0.2 / 24-August-2017 <o:p></o:p></span></h3>
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<span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.0.3 / 12-February-2021 <o:p></o:p></span></h3>
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<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
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Changes<o:p></o:p></span></u></b></p>
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<ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;">stm32746g_discovery_lcd.c:</span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Remove GPIO PIN 13 (LCD VSYNC) configuration from BSP_LCD_MspInit() API to avoid conflict with stm32746g_discovery_ts.c driver.<br></span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.0.2 / 24-August-2017 <o:p></o:p></span></h3>
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@@ -688,7 +783,7 @@ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-backgro
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visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/class/1734.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="font-size: 10pt; font-family: Verdana;"><a target="_blank" href="http://www.st.com/internet/mcu/family/141.jsp"><u><span style="color: blue;"></span></u></a></span><span style="font-size: 10pt; font-family: Verdana;"><u><span style="color: blue;"></span></u></span><span style="color: black;"><o:p></o:p></span></p>
689784
</td>
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</tr>
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</tbody>
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<tr><td style="padding: 0cm;" valign="top"></td></tr></tbody>
692787
</table>
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<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
694789
</td>

‎Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_lcd.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1325,7 +1325,7 @@ __weak void BSP_LCD_MspInit(LTDC_HandleTypeDef *hltdc, void *Params)
13251325

13261326
/* GPIOI LTDC alternate configuration */
13271327
gpio_init_structure.Pin = GPIO_PIN_9 | GPIO_PIN_10 | \
1328-
GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
1328+
GPIO_PIN_14 | GPIO_PIN_15;
13291329
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
13301330
gpio_init_structure.Alternate = GPIO_AF14_LTDC;
13311331
HAL_GPIO_Init(GPIOI, &gpio_init_structure);

‎Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f745xx.h‎

Lines changed: 31 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -475,7 +475,8 @@ typedef struct
475475
__IO uint32_t PTPTTLR;
476476
__IO uint32_t RESERVED8;
477477
__IO uint32_t PTPTSSR;
478-
uint32_t RESERVED9[565];
478+
__IO uint32_t PTPPPSCR;
479+
uint32_t RESERVED9[564];
479480
__IO uint32_t DMABMR;
480481
__IO uint32_t DMATPDR;
481482
__IO uint32_t DMARPDR;
@@ -12899,6 +12900,30 @@ typedef struct
1289912900
#define SYSCFG_MEMRMP_SWP_FMC_1 (0x2UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000800 */
1290012901

1290112902
/****************** Bit definition for SYSCFG_PMC register ******************/
12903+
#define SYSCFG_PMC_I2C1_FMP_Pos (0U)
12904+
#define SYSCFG_PMC_I2C1_FMP_Msk (0x1UL << SYSCFG_PMC_I2C1_FMP_Pos) /*!< 0x00000001 */
12905+
#define SYSCFG_PMC_I2C1_FMP SYSCFG_PMC_I2C1_FMP_Msk /*!< I2C1_FMP I2C1 Fast Mode + Enable */
12906+
#define SYSCFG_PMC_I2C2_FMP_Pos (1U)
12907+
#define SYSCFG_PMC_I2C2_FMP_Msk (0x1UL << SYSCFG_PMC_I2C2_FMP_Pos) /*!< 0x00000002 */
12908+
#define SYSCFG_PMC_I2C2_FMP SYSCFG_PMC_I2C2_FMP_Msk /*!< I2C2_FMP I2C2 Fast Mode + Enable */
12909+
#define SYSCFG_PMC_I2C3_FMP_Pos (2U)
12910+
#define SYSCFG_PMC_I2C3_FMP_Msk (0x1UL << SYSCFG_PMC_I2C3_FMP_Pos) /*!< 0x00000004 */
12911+
#define SYSCFG_PMC_I2C3_FMP SYSCFG_PMC_I2C3_FMP_Msk /*!< I2C3_FMP I2C3 Fast Mode + Enable */
12912+
#define SYSCFG_PMC_I2C4_FMP_Pos (3U)
12913+
#define SYSCFG_PMC_I2C4_FMP_Msk (0x1UL << SYSCFG_PMC_I2C4_FMP_Pos) /*!< 0x00000008 */
12914+
#define SYSCFG_PMC_I2C4_FMP SYSCFG_PMC_I2C4_FMP_Msk /*!< I2C4_FMP I2C4 Fast Mode + Enable */
12915+
#define SYSCFG_PMC_I2C_PB6_FMP_Pos (4U)
12916+
#define SYSCFG_PMC_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB6_FMP_Pos) /*!< 0x00000010 */
12917+
#define SYSCFG_PMC_I2C_PB6_FMP SYSCFG_PMC_I2C_PB6_FMP_Msk /*!< PB6_FMP Fast Mode + Enable */
12918+
#define SYSCFG_PMC_I2C_PB7_FMP_Pos (5U)
12919+
#define SYSCFG_PMC_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB7_FMP_Pos) /*!< 0x00000020 */
12920+
#define SYSCFG_PMC_I2C_PB7_FMP SYSCFG_PMC_I2C_PB7_FMP_Msk /*!< PB7_FMP Fast Mode + Enable */
12921+
#define SYSCFG_PMC_I2C_PB8_FMP_Pos (6U)
12922+
#define SYSCFG_PMC_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB8_FMP_Pos) /*!< 0x00000040 */
12923+
#define SYSCFG_PMC_I2C_PB8_FMP SYSCFG_PMC_I2C_PB8_FMP_Msk /*!< PB8_FMP Fast Mode + Enable */
12924+
#define SYSCFG_PMC_I2C_PB9_FMP_Pos (7U)
12925+
#define SYSCFG_PMC_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB9_FMP_Pos) /*!< 0x00000080 */
12926+
#define SYSCFG_PMC_I2C_PB9_FMP SYSCFG_PMC_I2C_PB9_FMP_Msk /*!< PB9_FMP Fast Mode + Enable */
1290212927

1290312928
#define SYSCFG_PMC_ADCxDC2_Pos (16U)
1290412929
#define SYSCFG_PMC_ADCxDC2_Msk (0x7UL << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */
@@ -15221,6 +15246,11 @@ typedef struct
1522115246
#define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
1522215247
#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
1522315248

15249+
/* Bit definition for Ethernet PTP PPS Control Register */
15250+
#define ETH_PTPPPSCR_PPSFREQ_Pos (0U)
15251+
#define ETH_PTPPPSCR_PPSFREQ_Msk (0x0FUL << ETH_PTPPPSCR_PPSFREQ_Pos) /*!< 0x0000000F */
15252+
#define ETH_PTPPPSCR_PPSFREQ ETH_PTPPPSCR_PPSFREQ_Msk /* PPS frequency selection */
15253+
1522415254
/******************************************************************************/
1522515255
/* Ethernet DMA Registers bits definition */
1522615256
/******************************************************************************/

‎Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h‎

Lines changed: 31 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -477,7 +477,8 @@ typedef struct
477477
__IO uint32_t PTPTTLR;
478478
__IO uint32_t RESERVED8;
479479
__IO uint32_t PTPTSSR;
480-
uint32_t RESERVED9[565];
480+
__IO uint32_t PTPPPSCR;
481+
uint32_t RESERVED9[564];
481482
__IO uint32_t DMABMR;
482483
__IO uint32_t DMATPDR;
483484
__IO uint32_t DMARPDR;
@@ -13247,6 +13248,30 @@ typedef struct
1324713248
#define SYSCFG_MEMRMP_SWP_FMC_1 (0x2UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000800 */
1324813249

1324913250
/****************** Bit definition for SYSCFG_PMC register ******************/
13251+
#define SYSCFG_PMC_I2C1_FMP_Pos (0U)
13252+
#define SYSCFG_PMC_I2C1_FMP_Msk (0x1UL << SYSCFG_PMC_I2C1_FMP_Pos) /*!< 0x00000001 */
13253+
#define SYSCFG_PMC_I2C1_FMP SYSCFG_PMC_I2C1_FMP_Msk /*!< I2C1_FMP I2C1 Fast Mode + Enable */
13254+
#define SYSCFG_PMC_I2C2_FMP_Pos (1U)
13255+
#define SYSCFG_PMC_I2C2_FMP_Msk (0x1UL << SYSCFG_PMC_I2C2_FMP_Pos) /*!< 0x00000002 */
13256+
#define SYSCFG_PMC_I2C2_FMP SYSCFG_PMC_I2C2_FMP_Msk /*!< I2C2_FMP I2C2 Fast Mode + Enable */
13257+
#define SYSCFG_PMC_I2C3_FMP_Pos (2U)
13258+
#define SYSCFG_PMC_I2C3_FMP_Msk (0x1UL << SYSCFG_PMC_I2C3_FMP_Pos) /*!< 0x00000004 */
13259+
#define SYSCFG_PMC_I2C3_FMP SYSCFG_PMC_I2C3_FMP_Msk /*!< I2C3_FMP I2C3 Fast Mode + Enable */
13260+
#define SYSCFG_PMC_I2C4_FMP_Pos (3U)
13261+
#define SYSCFG_PMC_I2C4_FMP_Msk (0x1UL << SYSCFG_PMC_I2C4_FMP_Pos) /*!< 0x00000008 */
13262+
#define SYSCFG_PMC_I2C4_FMP SYSCFG_PMC_I2C4_FMP_Msk /*!< I2C4_FMP I2C4 Fast Mode + Enable */
13263+
#define SYSCFG_PMC_I2C_PB6_FMP_Pos (4U)
13264+
#define SYSCFG_PMC_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB6_FMP_Pos) /*!< 0x00000010 */
13265+
#define SYSCFG_PMC_I2C_PB6_FMP SYSCFG_PMC_I2C_PB6_FMP_Msk /*!< PB6_FMP Fast Mode + Enable */
13266+
#define SYSCFG_PMC_I2C_PB7_FMP_Pos (5U)
13267+
#define SYSCFG_PMC_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB7_FMP_Pos) /*!< 0x00000020 */
13268+
#define SYSCFG_PMC_I2C_PB7_FMP SYSCFG_PMC_I2C_PB7_FMP_Msk /*!< PB7_FMP Fast Mode + Enable */
13269+
#define SYSCFG_PMC_I2C_PB8_FMP_Pos (6U)
13270+
#define SYSCFG_PMC_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB8_FMP_Pos) /*!< 0x00000040 */
13271+
#define SYSCFG_PMC_I2C_PB8_FMP SYSCFG_PMC_I2C_PB8_FMP_Msk /*!< PB8_FMP Fast Mode + Enable */
13272+
#define SYSCFG_PMC_I2C_PB9_FMP_Pos (7U)
13273+
#define SYSCFG_PMC_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB9_FMP_Pos) /*!< 0x00000080 */
13274+
#define SYSCFG_PMC_I2C_PB9_FMP SYSCFG_PMC_I2C_PB9_FMP_Msk /*!< PB9_FMP Fast Mode + Enable */
1325013275

1325113276
#define SYSCFG_PMC_ADCxDC2_Pos (16U)
1325213277
#define SYSCFG_PMC_ADCxDC2_Msk (0x7UL << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */
@@ -15569,6 +15594,11 @@ typedef struct
1556915594
#define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
1557015595
#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
1557115596

15597+
/* Bit definition for Ethernet PTP PPS Control Register */
15598+
#define ETH_PTPPPSCR_PPSFREQ_Pos (0U)
15599+
#define ETH_PTPPPSCR_PPSFREQ_Msk (0x0FUL << ETH_PTPPPSCR_PPSFREQ_Pos) /*!< 0x0000000F */
15600+
#define ETH_PTPPPSCR_PPSFREQ ETH_PTPPPSCR_PPSFREQ_Msk /* PPS frequency selection */
15601+
1557215602
/******************************************************************************/
1557315603
/* Ethernet DMA Registers bits definition */
1557415604
/******************************************************************************/

‎Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f750xx.h‎

Lines changed: 31 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -478,7 +478,8 @@ typedef struct
478478
__IO uint32_t PTPTTLR;
479479
__IO uint32_t RESERVED8;
480480
__IO uint32_t PTPTSSR;
481-
uint32_t RESERVED9[565];
481+
__IO uint32_t PTPPPSCR;
482+
uint32_t RESERVED9[564];
482483
__IO uint32_t DMABMR;
483484
__IO uint32_t DMATPDR;
484485
__IO uint32_t DMARPDR;
@@ -13540,6 +13541,30 @@ typedef struct
1354013541
#define SYSCFG_MEMRMP_SWP_FMC_1 (0x2UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000800 */
1354113542

1354213543
/****************** Bit definition for SYSCFG_PMC register ******************/
13544+
#define SYSCFG_PMC_I2C1_FMP_Pos (0U)
13545+
#define SYSCFG_PMC_I2C1_FMP_Msk (0x1UL << SYSCFG_PMC_I2C1_FMP_Pos) /*!< 0x00000001 */
13546+
#define SYSCFG_PMC_I2C1_FMP SYSCFG_PMC_I2C1_FMP_Msk /*!< I2C1_FMP I2C1 Fast Mode + Enable */
13547+
#define SYSCFG_PMC_I2C2_FMP_Pos (1U)
13548+
#define SYSCFG_PMC_I2C2_FMP_Msk (0x1UL << SYSCFG_PMC_I2C2_FMP_Pos) /*!< 0x00000002 */
13549+
#define SYSCFG_PMC_I2C2_FMP SYSCFG_PMC_I2C2_FMP_Msk /*!< I2C2_FMP I2C2 Fast Mode + Enable */
13550+
#define SYSCFG_PMC_I2C3_FMP_Pos (2U)
13551+
#define SYSCFG_PMC_I2C3_FMP_Msk (0x1UL << SYSCFG_PMC_I2C3_FMP_Pos) /*!< 0x00000004 */
13552+
#define SYSCFG_PMC_I2C3_FMP SYSCFG_PMC_I2C3_FMP_Msk /*!< I2C3_FMP I2C3 Fast Mode + Enable */
13553+
#define SYSCFG_PMC_I2C4_FMP_Pos (3U)
13554+
#define SYSCFG_PMC_I2C4_FMP_Msk (0x1UL << SYSCFG_PMC_I2C4_FMP_Pos) /*!< 0x00000008 */
13555+
#define SYSCFG_PMC_I2C4_FMP SYSCFG_PMC_I2C4_FMP_Msk /*!< I2C4_FMP I2C4 Fast Mode + Enable */
13556+
#define SYSCFG_PMC_I2C_PB6_FMP_Pos (4U)
13557+
#define SYSCFG_PMC_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB6_FMP_Pos) /*!< 0x00000010 */
13558+
#define SYSCFG_PMC_I2C_PB6_FMP SYSCFG_PMC_I2C_PB6_FMP_Msk /*!< PB6_FMP Fast Mode + Enable */
13559+
#define SYSCFG_PMC_I2C_PB7_FMP_Pos (5U)
13560+
#define SYSCFG_PMC_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB7_FMP_Pos) /*!< 0x00000020 */
13561+
#define SYSCFG_PMC_I2C_PB7_FMP SYSCFG_PMC_I2C_PB7_FMP_Msk /*!< PB7_FMP Fast Mode + Enable */
13562+
#define SYSCFG_PMC_I2C_PB8_FMP_Pos (6U)
13563+
#define SYSCFG_PMC_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB8_FMP_Pos) /*!< 0x00000040 */
13564+
#define SYSCFG_PMC_I2C_PB8_FMP SYSCFG_PMC_I2C_PB8_FMP_Msk /*!< PB8_FMP Fast Mode + Enable */
13565+
#define SYSCFG_PMC_I2C_PB9_FMP_Pos (7U)
13566+
#define SYSCFG_PMC_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB9_FMP_Pos) /*!< 0x00000080 */
13567+
#define SYSCFG_PMC_I2C_PB9_FMP SYSCFG_PMC_I2C_PB9_FMP_Msk /*!< PB9_FMP Fast Mode + Enable */
1354313568

1354413569
#define SYSCFG_PMC_ADCxDC2_Pos (16U)
1354513570
#define SYSCFG_PMC_ADCxDC2_Msk (0x7UL << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */
@@ -15862,6 +15887,11 @@ typedef struct
1586215887
#define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
1586315888
#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
1586415889

15890+
/* Bit definition for Ethernet PTP PPS Control Register */
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#define ETH_PTPPPSCR_PPSFREQ_Pos (0U)
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#define ETH_PTPPPSCR_PPSFREQ_Msk (0x0FUL << ETH_PTPPPSCR_PPSFREQ_Pos) /*!< 0x0000000F */
15893+
#define ETH_PTPPPSCR_PPSFREQ ETH_PTPPPSCR_PPSFREQ_Msk /* PPS frequency selection */
15894+
1586515895
/******************************************************************************/
1586615896
/* Ethernet DMA Registers bits definition */
1586715897
/******************************************************************************/

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