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Erwan Le RayADESTM
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serial: stm32: move RX dma initialization to startup
The RX dma channel is kept active forever (from the probe). That prevents going to low power mode when it is used. So move the configuration and enabling/disabling procedures to the startup/shutdown routines. Signed-off-by: Erwan Le Ray <erwan.leray@st.com> Change-Id: Ia06918fbdd07d04e4f5bb8d54a2a5841e0bf6f3d Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/linux-stm32/+/155437 Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com> Reviewed-by: CIBUILD <smet-aci-builds@lists.codex.cro.st.com> Reviewed-by: Fabrice GASNIER <fabrice.gasnier@st.com>
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drivers/tty/serial/stm32-usart.c

Lines changed: 30 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -692,6 +692,8 @@ static int stm32_startup(struct uart_port *port)
692692
struct stm32_port *stm32_port = to_stm32_port(port);
693693
struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
694694
const char *name = to_platform_device(port->dev)->name;
695+
struct dma_async_tx_descriptor *desc = NULL;
696+
dma_cookie_t cookie;
695697
u32 val;
696698
int ret;
697699

@@ -705,6 +707,29 @@ static int stm32_startup(struct uart_port *port)
705707
if (ofs->rqr != UNDEF_REG)
706708
stm32_set_bits(port, ofs->rqr, USART_RQR_RXFRQ);
707709

710+
if (stm32_port->rx_ch) {
711+
stm32_port->last_res = RX_BUF_L;
712+
/* Prepare a DMA cyclic transaction */
713+
desc = dmaengine_prep_dma_cyclic(stm32_port->rx_ch,
714+
stm32_port->rx_dma_buf,
715+
RX_BUF_L, RX_BUF_P,
716+
DMA_DEV_TO_MEM,
717+
DMA_PREP_INTERRUPT);
718+
if (!desc) {
719+
dev_err(port->dev, "rx dma prep cyclic failed\n");
720+
return -ENODEV;
721+
}
722+
723+
desc->callback = stm32_rx_dma_complete;
724+
desc->callback_param = port;
725+
726+
/* Push current DMA transaction in the pending queue */
727+
cookie = dmaengine_submit(desc);
728+
729+
/* Issue pending DMA requests */
730+
dma_async_issue_pending(stm32_port->rx_ch);
731+
}
732+
708733
/* RX enabling */
709734
val = stm32_port->cr1_irq | USART_CR1_RE;
710735
stm32_set_bits(port, ofs->cr1, val);
@@ -740,6 +765,9 @@ static void stm32_shutdown(struct uart_port *port)
740765
stm32_clr_bits(port, ofs->cr3,
741766
USART_CR3_TXFTIE | USART_CR3_RXFTIE);
742767

768+
if (stm32_port->rx_ch)
769+
dmaengine_terminate_async(stm32_port->rx_ch);
770+
743771
free_irq(port->irq, port);
744772
}
745773

@@ -1165,8 +1193,6 @@ static int stm32_of_dma_rx_probe(struct stm32_port *stm32port,
11651193
struct uart_port *port = &stm32port->port;
11661194
struct device *dev = &pdev->dev;
11671195
struct dma_slave_config config;
1168-
struct dma_async_tx_descriptor *desc = NULL;
1169-
dma_cookie_t cookie;
11701196
int ret;
11711197

11721198
/* Request DMA RX channel */
@@ -1195,26 +1221,6 @@ static int stm32_of_dma_rx_probe(struct stm32_port *stm32port,
11951221
goto config_err;
11961222
}
11971223

1198-
/* Prepare a DMA cyclic transaction */
1199-
desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch,
1200-
stm32port->rx_dma_buf,
1201-
RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM,
1202-
DMA_PREP_INTERRUPT);
1203-
if (!desc) {
1204-
dev_err(dev, "rx dma prep cyclic failed\n");
1205-
ret = -ENODEV;
1206-
goto config_err;
1207-
}
1208-
1209-
desc->callback = stm32_rx_dma_complete;
1210-
desc->callback_param = port;
1211-
1212-
/* Push current DMA transaction in the pending queue */
1213-
cookie = dmaengine_submit(desc);
1214-
1215-
/* Issue pending DMA requests */
1216-
dma_async_issue_pending(stm32port->rx_ch);
1217-
12181224
return 0;
12191225

12201226
config_err:
@@ -1335,10 +1341,8 @@ static int stm32_serial_probe(struct platform_device *pdev)
13351341
return 0;
13361342

13371343
err_dma:
1338-
if (stm32port->rx_ch) {
1339-
dmaengine_terminate_async(stm32port->rx_ch);
1344+
if (stm32port->rx_ch)
13401345
dma_release_channel(stm32port->rx_ch);
1341-
}
13421346

13431347
if (stm32port->rx_dma_buf)
13441348
dma_free_coherent(&pdev->dev,
@@ -1387,10 +1391,8 @@ static int stm32_serial_remove(struct platform_device *pdev)
13871391
cr3 &= ~USART_CR3_DDRE;
13881392
writel_relaxed(cr3, port->membase + ofs->cr3);
13891393

1390-
if (stm32_port->rx_ch) {
1391-
dmaengine_terminate_async(stm32_port->rx_ch);
1394+
if (stm32_port->rx_ch)
13921395
dma_release_channel(stm32_port->rx_ch);
1393-
}
13941396

13951397
if (stm32_port->rx_dma_buf)
13961398
dma_free_coherent(&pdev->dev,

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