usb: dwc2: defer probe in case of core reset failure

Normally the core reset can take several clocks, depending on the current
state of the core. After this bit is cleared, the application must wait at
least 3 PHY clocks before doing any access to the PHY domain
(synchronization delay).
But on STM32MP15, after the 10ms delay, the bit is still not cleared. The
reason is not known right now, so, the proposal is to defer probe when the
issue occurs.

Change-Id: I6bb7624f649bdf5fd5663311fd25e3f1af518946
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/linux-stm32/+/168068
Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: Fabrice GASNIER <fabrice.gasnier@st.com>

Author: ADESTM

drivers/usb/dwc2/platform.c

@@ -450,8 +450,11 @@ static int dwc2_driver_probe(struct platform_device *dev)
 	 * reset value form registers.
 	 */
 	retval = dwc2_core_reset(hsotg, false);
-	if (retval)
+	if (retval) {
+		/* TEMPORARY WORKAROUND */
+		retval = -EPROBE_DEFER;
 		goto error;
+	}
 
 	/* Detect config values from hardware */
 	retval = dwc2_get_hwparams(hsotg);