iio: adc: stm32-adc: fix a race when using several adcs with dma and irq

End of conversion may be handled by using IRQ or DMA. There may be a
race when two conversions complete at the same time on several ADCs.
EOC can be read as 'set' for several ADCs, with:
- an ADC configured to use IRQs. EOCIE bit is set. The handler in normally
  called in this case.
- an ADC configured to use DMA. EOCIE bit isn't set. EOC triggers the DMA
  request instead. It's then automatically cleared by DMA read. But the
  handler gets called due to status bit is temporarily set (IRQ triggered
  by the other ADC).
So both EOC status bit in CSR and EOCIE control bit must be checked
before invoking the interrupt handler (e.g. call ISR only for
IRQ-enabled ADCs).

Fixes: 2763ea0 ("iio: adc: stm32: add optional dma support")

Change-Id: I148ca98184bf6b63d2bd0e3bfc0c1f423c16ba68
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/linux-stm32/+/141381
Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: CIBUILD <smet-aci-builds@lists.codex.cro.st.com>

Author: Fabrice Gasnier

drivers/iio/adc/stm32-adc-core.c

@@ -102,6 +102,8 @@
  * @jeoc1:	adc1 end of injected conversion flag in @csr
  * @jeoc2:	adc2 end of injected conversion flag in @csr
  * @jeoc3:	adc3 end of injected conversion flag in @csr
+ * @ier:	interrupt enable register offset for each adc
+ * @eocie_msk:	end of conversion interrupt enable mask in @ier
  */
 struct stm32_adc_common_regs {
 	u32 csr;
@@ -112,6 +114,8 @@ struct stm32_adc_common_regs {
 	u32 jeoc1_msk;
 	u32 jeoc2_msk;
 	u32 jeoc3_msk;
+	u32 ier;
+	u32 eocie_msk;
 };
 
 struct stm32_adc_priv;
@@ -354,6 +358,8 @@ static const struct stm32_adc_common_regs stm32f4_adc_common_regs = {
 	.jeoc1_msk = STM32F4_JEOC_MASK1,
 	.jeoc2_msk = STM32F4_JEOC_MASK2,
 	.jeoc3_msk = STM32F4_JEOC_MASK3,
+	.ier = STM32F4_ADC_CR1,
+	.eocie_msk = STM32F4_EOCIE,
 };
 
 /* STM32H7 common registers definitions */
@@ -364,8 +370,24 @@ static const struct stm32_adc_common_regs stm32h7_adc_common_regs = {
 	.eoc2_msk = STM32H7_EOC_MASK2,
 	.jeoc1_msk = STM32H7_JEOC_MASK1,
 	.jeoc2_msk = STM32H7_JEOC_MASK2,
+	.ier = STM32H7_ADC_IER,
+	.eocie_msk = STM32H7_EOCIE,
 };
 
+static const unsigned int stm32_adc_offset[STM32_ADC_MAX_ADCS] = {
+	0, STM32_ADC_OFFSET, STM32_ADC_OFFSET * 2,
+};
+
+static unsigned int stm32_adc_eoc_enabled(struct stm32_adc_priv *priv,
+					  unsigned int adc)
+{
+	u32 ier, offset = stm32_adc_offset[adc];
+
+	ier = readl_relaxed(priv->common.base + offset + priv->cfg->regs->ier);
+
+	return ier & priv->cfg->regs->eocie_msk;
+}
+
 /* ADC common interrupt for all instances */
 static void stm32_adc_irq_handler(struct irq_desc *desc)
 {
@@ -376,13 +398,28 @@ static void stm32_adc_irq_handler(struct irq_desc *desc)
 	chained_irq_enter(chip, desc);
 	status = readl_relaxed(priv->common.base + priv->cfg->regs->csr);
 
-	if (status & priv->cfg->regs->eoc1_msk)
+	/*
+	 * End of conversion may be handled by using IRQ or DMA. There may be a
+	 * race here when two conversions complete at the same time on several
+	 * ADCs. EOC may be read 'set' for several ADCs, with:
+	 * - an ADC configured to use DMA (EOC triggers the DMA request, and
+	 *   is then automatically cleared by DR read in hardware)
+	 * - an ADC configured to use IRQs (EOCIE bit is set. The handler must
+	 *   be called in this case)
+	 * So both EOC status bit in CSR and EOCIE control bit must be checked
+	 * before invoking the interrupt handler (e.g. call ISR only for
+	 * IRQ-enabled ADCs).
+	 */
+	if (status & priv->cfg->regs->eoc1_msk &&
+	    stm32_adc_eoc_enabled(priv, 0))
 		generic_handle_irq(irq_find_mapping(priv->domain, 0));
 
-	if (status & priv->cfg->regs->eoc2_msk)
+	if (status & priv->cfg->regs->eoc2_msk &&
+	    stm32_adc_eoc_enabled(priv, 1))
 		generic_handle_irq(irq_find_mapping(priv->domain, 1));
 
-	if (status & priv->cfg->regs->eoc3_msk)
+	if (status & priv->cfg->regs->eoc3_msk &&
+	    stm32_adc_eoc_enabled(priv, 2))
 		generic_handle_irq(irq_find_mapping(priv->domain, 2));
 
 	if (status & priv->cfg->regs->jeoc1_msk)

drivers/iio/adc/stm32-adc-core.h

@@ -45,12 +45,24 @@ struct stm32_adc_calib {
 	bool			calibrated;
 };
 
+/* STM32F4 - registers for each ADC instance */
+#define STM32F4_ADC_CR1			0x04
+
+/* STM32F4_ADC_CR1 - bit fields */
+#define STM32F4_EOCIE			BIT(5)
+
 /* STM32F4 - common registers for all ADC instances: 1, 2 & 3 */
 #define STM32F4_ADC_CCR			(STM32_ADCX_COMN_OFFSET + 0x04)
 
 /* STM32F4_ADC_CCR - bit fields */
 #define STM32F4_ADC_TSVREFE		BIT(23)
 
+/* STM32H7 - registers for each instance */
+#define STM32H7_ADC_IER			0x04
+
+/* STM32H7_ADC_IER - bit fields */
+#define STM32H7_EOCIE			BIT(2)
+
 /* STM32H7 - common registers for all ADC instances */
 #define STM32H7_ADC_CCR			(STM32_ADCX_COMN_OFFSET + 0x08)
 

drivers/iio/adc/stm32-adc.c

@@ -32,7 +32,6 @@
 
 /* STM32F4 - Registers for each ADC instance */
 #define STM32F4_ADC_SR			0x00
-#define STM32F4_ADC_CR1			0x04
 #define STM32F4_ADC_CR2			0x08
 #define STM32F4_ADC_SMPR1		0x0C
 #define STM32F4_ADC_SMPR2		0x10
@@ -66,7 +65,6 @@
 #define STM32F4_SCAN			BIT(8)
 #define STM32F4_JEOCIE			BIT(7)
 #define STM32F4_AWDIE			BIT(6)
-#define STM32F4_EOCIE			BIT(5)
 #define STM32F4_AWDCH_SHIFT		0
 #define STM32F4_AWDCH_MASK		GENMASK(4, 0)
 
@@ -88,7 +86,6 @@
 
 /* STM32H7 - Registers for each ADC instance */
 #define STM32H7_ADC_ISR			0x00
-#define STM32H7_ADC_IER			0x04
 #define STM32H7_ADC_CR			0x08
 #define STM32H7_ADC_CFGR		0x0C
 #define STM32H7_ADC_SMPR1		0x14
@@ -132,7 +129,6 @@
 #define STM32H7_AWD1IE			STM32H7_AWD1
 #define STM32H7_JEOSIE			STM32H7_JEOS
 #define STM32H7_OVRIE			STM32H7_OVR
-#define STM32H7_EOCIE			STM32H7_EOC
 
 /* STM32H7_ADC_CR - bit fields */
 #define STM32H7_ADCAL			BIT(31)