@@ -50035,28 +50035,6 @@ static bool hasBZHI(const X86Subtarget &Subtarget, MVT VT) {
5003550035 (VT == MVT::i32 || (VT == MVT::i64 && Subtarget.is64Bit()));
5003650036}
5003750037
50038- /// Folds (and X, (or Y, ~Z)) --> (and X, ~(and ~Y, Z))
50039- /// This undoes the inverse fold performed in InstCombine
50040- static SDValue combineAndNotOrIntoAndNotAnd(SDNode *N, SelectionDAG &DAG) {
50041-
50042- using namespace llvm::SDPatternMatch;
50043- MVT VT = N->getSimpleValueType(0);
50044- SDLoc DL(N);
50045- const TargetLowering &TLI = DAG.getTargetLoweringInfo();
50046- if (!TLI.hasAndNot(SDValue(N, 0)))
50047- return SDValue();
50048-
50049- SDValue X, Y, Z;
50050- if (sd_match(
50051- N, m_And(m_Value(X), m_OneUse(m_Or(m_Value(Y), m_Not(m_Value(Z)))))))
50052- return DAG.getNode(
50053- ISD::AND, DL, VT, X,
50054- DAG.getNOT(DL, DAG.getNode(ISD::AND, DL, VT, DAG.getNOT(DL, Y, VT), Z),
50055- VT));
50056-
50057- return SDValue();
50058- }
50059-
5006050038// This function recognizes cases where X86 bzhi instruction can replace and
5006150039// 'and-load' sequence.
5006250040// In case of loading integer value from an array of constants which is defined
@@ -50548,9 +50526,6 @@ static SDValue combineAnd(SDNode *N, SelectionDAG &DAG,
5054850526 if (SDValue R = combineAndLoadToBZHI(N, DAG, Subtarget))
5054950527 return R;
5055050528
50551- if (SDValue R = combineAndNotOrIntoAndNotAnd(N, DAG))
50552- return R;
50553-
5055450529 // fold (and (mul x, c1), c2) -> (mul x, (and c1, c2))
5055550530 // iff c2 is all/no bits mask - i.e. a select-with-zero mask.
5055650531 // TODO: Handle PMULDQ/PMULUDQ/VPMADDWD/VPMADDUBSW?
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