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Author: Sameeranjoshi

llvm/lib/Target/AIE/AIELegalizerHelper.cpp

@@ -1377,21 +1377,24 @@ bool AIELegalizerHelper::legalizeG_FADD_G_FSUB(LegalizerHelper &Helper,
   const LLT SrcLHSTy = MRI.getType(SrcLHS);
   const LLT SrcRHSTy = MRI.getType(SrcRHS);
 
-  // Handle bf16 vectors code assumes the input is <32 x bf16>, the LegalizerInfo makes 
-  // sure that the input is either padded or unmerged to <32 x bf16>.
+  // Handle bf16 vectors code assumes the input is <32 x bf16>, the
+  // LegalizerInfo makes sure that the input is either padded or unmerged to <32
+  // x bf16>.
   if (isBF16Vector(SrcLHSTy) && isBF16Vector(SrcRHSTy)) {
     // vector should be of size 32 asssert
-    assert(SrcLHSTy.getNumElements() == 32 && SrcRHSTy.getNumElements() == 32 && 
-    "Expected vector of size 32 for inputs of G_FADD/G_FSUB");
+    assert(SrcLHSTy.getNumElements() == 32 && SrcRHSTy.getNumElements() == 32 &&
+           "Expected vector of size 32 for inputs of G_FADD/G_FSUB");
 
-    // Step 2: Convert bf16 vectors to f32 vectors using FPExt
-    const LLT F32VecTy = LLT::fixed_vector(SrcLHSTy.getNumElements(), LLT::scalar(32));
+    // Step 1: Convert bf16 vectors to f32 vectors using FPExt
+    const LLT F32VecTy =
+        LLT::fixed_vector(SrcLHSTy.getNumElements(), LLT::scalar(32));
     Register SrcLHSF32 = MRI.createGenericVirtualRegister(F32VecTy);
     Register SrcRHSF32 = MRI.createGenericVirtualRegister(F32VecTy);
     MIRBuilder.buildFPExt(SrcLHSF32, SrcLHS);
     MIRBuilder.buildFPExt(SrcRHSF32, SrcRHS);
-    
-    // Step 3: Input is going to be <32 x bf16> pad it to <64 x f32> for AIE2P as AccV64S32 is legal on AIE2P.
+
+    // Step 2: Input is going to be <32 x bf16> pad it to <64 x f32> for AIE2P
+    // as AccV64S32 is legal on AIE2P.
     if (ST.isAIE2P()) {
       const Register UndefVec = MIRBuilder.buildUndef(F32VecTy).getReg(0);
       const Register ConcatLHS = MRI.createGenericVirtualRegister(V64FP32);
@@ -1401,35 +1404,41 @@ bool AIELegalizerHelper::legalizeG_FADD_G_FSUB(LegalizerHelper &Helper,
       SrcLHSF32 = ConcatLHS;
       SrcRHSF32 = ConcatRHS;
     }
-    
-    // Step 4: Perform the floating point operation
-    Register Res = MIRBuilder.buildInstr(MI.getOpcode(), {MRI.getType(SrcLHSF32)}, {SrcLHSF32, SrcRHSF32}).getReg(0);
-    
-    // Step 5: Handle accumulator conversion based on target
+
+    // Step 3: Perform the floating point operation
+    Register Res = MIRBuilder
+                       .buildInstr(MI.getOpcode(), {MRI.getType(SrcLHSF32)},
+                                   {SrcLHSF32, SrcRHSF32})
+                       .getReg(0);
+
+    // Step 4: Handle accumulator conversion based on target
     if (ST.isAIE2()) {
       Res = MIRBuilder.buildBitcast(V8ACC64, Res).getReg(0);
     } else if (ST.isAIE2P()) {
       // Unmerge to get 2 vectors of <32xf32> as FADD/FSUB was done on <64xf32>
       SmallVector<Register, 2> UnmergedRegs;
       const auto Unmerge = MIRBuilder.buildUnmerge(F32VecTy, Res);
       getUnmergeResults(UnmergedRegs, *Unmerge);
-      Res = UnmergedRegs[0]; // Take the first <32xf32> vector, other half is just zeros.
+      Res = UnmergedRegs[0]; // Take the first <32xf32> vector, other half is
+                             // just zeros.
     }
-    
-    // Step 6: Convert back to bf16 using the truncation intrinsic
+
+    // Step 5: Convert back to bf16 using the truncation intrinsic
     const int VecSize = MRI.getType(Res).getSizeInBits();
     const LLT DstLLT = ST.isAIE2P() ? V32BF16 : V16BF16;
-    Res = MIRBuilder.buildIntrinsic(getFpTrunc32ToBF16IntrID(ST, VecSize), {DstLLT}, true, false)
+    Res = MIRBuilder
+              .buildIntrinsic(getFpTrunc32ToBF16IntrID(ST, VecSize), {DstLLT},
+                              true, false)
               .addUse(Res)
               .getReg(0);
-    
+
     // Handle AIE2 padding
     if (ST.isAIE2()) {
       Res = emitPadUndefVector(MRI, MIRBuilder, V32BF16, Res);
     }
-    
+
     MIRBuilder.buildCopy(DstReg, Res);
-    
+
     MI.eraseFromParent();
     return true;
   }

llvm/lib/Target/AIE/aie2p/AIE2PLegalizerInfo.cpp

@@ -277,7 +277,9 @@ AIE2PLegalizerInfo::AIE2PLegalizerInfo(const AIE2PSubtarget &ST)
       .moreElementsIf(
           [=](const LegalityQuery &Query) {
             const LLT &Ty = Query.Types[0];
-            return Ty.isVector() && (Ty.getScalarSizeInBits() == 32 || Ty.getScalarSizeInBits() == 16) &&
+            return Ty.isVector() &&
+                   (Ty.getScalarSizeInBits() == 32 ||
+                    Ty.getScalarSizeInBits() == 16) &&
                    Ty.getNumElements() < 32;
           },
           [=](const LegalityQuery &Query) {