-
Notifications
You must be signed in to change notification settings - Fork 49
Description
pyvcd only supports dumping the size of the signal, where size can be an integer or a sequence of integers:
Lines 125 to 132 in 0890733
| def register_var( | |
| self, | |
| scope: ScopeInput, | |
| name: str, | |
| var_type: Union[VarType, str], | |
| size: Optional[VariableSize] = None, | |
| init: VarValue = None, | |
| ) -> "Variable": |
This leads to an output similar to:
$var wire 5 $ signal $end
VCD also supports providing a slice next to the signal's name:
Excerpt from Syntax 21-20—Syntax for output 4-state VCD file (LRM 2023)
reference ::= identifier
| identifier [ bit_select_index ]
| identifier [ msb_index : lsb_index ]
declaration_command ::=
...
| $var [ var_type size identifier_code reference ] $end
...
size ::= decimal_number
bit_select_index and [ msb_index : lsb_index ] are used to dump individual bits of a vector.
Additionally, identifier [ msb_index : lsb_index ] can be used to specify the integer and fractional parts of a fixed point number, which enables automatic value representation in a waveform viewer, e.g.:
$var wire 5 $ signal[2:-2] $end
For example surfer-project uses this.
register_var could be augmented to support specific ranges. Does this make sense, and would the code owners be interested in this feature?
Background: I work with a design with fixed point numbers in Amaranth HDL, which uses pyvcd.