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ChrisRackauckasChrisRackauckas
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Merge pull request #2831 from ChrisRackauckas-Claude/add-simd-rk-sublibrary
Add OrdinaryDiffEqSIMDRK as a standalone sublibrary
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‎.github/workflows/CI.yml‎

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- OrdinaryDiffEqRKN
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- OrdinaryDiffEqRosenbrock
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- OrdinaryDiffEqSDIRK
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- OrdinaryDiffEqSIMDRK
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- OrdinaryDiffEqSSPRK
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- OrdinaryDiffEqStabilizedIRK
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- OrdinaryDiffEqStabilizedRK

‎lib/OrdinaryDiffEqSIMDRK/LICENSE.md‎

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MIT License
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Copyright (c) 2022 Yingbo Ma <[email protected]> and contributors
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.

‎lib/OrdinaryDiffEqSIMDRK/Project.toml‎

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name = "OrdinaryDiffEqSIMDRK"
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uuid = "dc97f408-7a72-40e4-9b0d-228a53b292f8"
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authors = ["Yingbo Ma <[email protected]>", "Chris Elrod <[email protected]>"]
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version = "1.0.0"
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[deps]
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MuladdMacro = "46d2c3a1-f734-5fdb-9937-b9b9aeba4221"
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OrdinaryDiffEqCore = "bbf590c4-e513-4bbe-9b18-05decba2e5d8"
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Reexport = "189a3867-3050-52da-a836-e630ba90ab69"
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SLEEFPirates = "476501e8-09a2-5ece-8869-fb82de89a1fa"
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Static = "aedffcd0-7271-4cad-89d0-dc628f76c6d3"
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UnPack = "3a884ed6-31ef-47d7-9d2a-63182c4928ed"
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VectorizationBase = "3d5dd08c-fd9d-11e8-17fa-ed2836048c2f"
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[compat]
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DiffEqDevTools = "2.44"
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MuladdMacro = "0.2"
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OrdinaryDiffEqCore = "1"
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Reexport = "1"
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SafeTestsets = "0.1"
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SLEEFPirates = "0.6"
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Static = "0.7, 0.8, 1"
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StaticArrays = "1.9"
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Test = "1"
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UnPack = "1"
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VectorizationBase = "0.21"
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julia = "1.10"
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[extras]
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DiffEqDevTools = "f3b72e0c-5b89-59e1-b016-84e28bfd966d"
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SafeTestsets = "1bc83da4-3b8d-516f-aca4-4fe02f6d838f"
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StaticArrays = "90137ffa-7385-5640-81b9-e52037218182"
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Test = "8dfed614-e22c-5e08-85e1-65c5234f0b40"
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[targets]
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test = ["DiffEqDevTools", "SafeTestsets", "StaticArrays", "Test"]
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[sources.OrdinaryDiffEqCore]
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path = "../OrdinaryDiffEqCore"

‎lib/OrdinaryDiffEqSIMDRK/src/OrdinaryDiffEqSIMDRK.jl‎

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module OrdinaryDiffEqSIMDRK
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using MuladdMacro, UnPack, Static
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using OrdinaryDiffEqCore: OrdinaryDiffEqAdaptiveAlgorithm, OrdinaryDiffEqConstantCache,
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trivial_limiter!, calculate_residuals, constvalue
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import OrdinaryDiffEqCore: initialize!, perform_step!, alg_cache
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using Reexport: @reexport
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@reexport using OrdinaryDiffEqCore
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include("algorithms.jl")
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include("caches.jl")
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include("perform_step.jl")
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export MER5v2, MER6v2, RK6v4
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end

‎lib/OrdinaryDiffEqSIMDRK/src/algorithms.jl‎

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struct MER5v2{StageLimiter, StepLimiter, Thread} <: OrdinaryDiffEqAdaptiveAlgorithm
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stage_limiter!::StageLimiter
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step_limiter!::StepLimiter
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thread::Thread
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end
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function MER5v2(; stage_limiter! = trivial_limiter!, step_limiter! = trivial_limiter!,
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thread = False())
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MER5v2{typeof(stage_limiter!), typeof(step_limiter!), typeof(thread)}(stage_limiter!,
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step_limiter!,
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thread)
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end
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# for backwards compatibility
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function MER5v2(stage_limiter!, step_limiter! = trivial_limiter!)
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MER5v2{typeof(stage_limiter!), typeof(step_limiter!), False}(stage_limiter!,
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step_limiter!, False())
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end
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struct MER6v2{StageLimiter, StepLimiter, Thread} <: OrdinaryDiffEqAdaptiveAlgorithm
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stage_limiter!::StageLimiter
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step_limiter!::StepLimiter
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thread::Thread
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end
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function MER6v2(; stage_limiter! = trivial_limiter!, step_limiter! = trivial_limiter!,
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thread = False())
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MER6v2{typeof(stage_limiter!), typeof(step_limiter!), typeof(thread)}(stage_limiter!,
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step_limiter!,
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thread)
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end
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# for backwards compatibility
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function MER6v2(stage_limiter!, step_limiter! = trivial_limiter!)
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MER6v2{typeof(stage_limiter!), typeof(step_limiter!), False}(stage_limiter!,
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step_limiter!, False())
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end
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struct RK6v4{StageLimiter, StepLimiter, Thread} <: OrdinaryDiffEqAdaptiveAlgorithm
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stage_limiter!::StageLimiter
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step_limiter!::StepLimiter
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thread::Thread
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end
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function RK6v4(; stage_limiter! = trivial_limiter!, step_limiter! = trivial_limiter!,
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thread = False())
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RK6v4{typeof(stage_limiter!), typeof(step_limiter!), typeof(thread)}(stage_limiter!,
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step_limiter!,
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thread)
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end
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# for backwards compatibility
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function RK6v4(stage_limiter!, step_limiter! = trivial_limiter!)
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RK6v4{typeof(stage_limiter!), typeof(step_limiter!), False}(stage_limiter!,
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step_limiter!, False())
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end
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function Base.show(io::IO, alg::Union{MER5v2, MER6v2, RK6v4})
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print(io, "$(nameof(typeof(alg)))(stage_limiter! = ", alg.stage_limiter!,
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", step_limiter! = ", alg.step_limiter!,
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", thread = ", alg.thread, ")")
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end
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OrdinaryDiffEqCore.alg_order(alg::MER5v2) = 5
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OrdinaryDiffEqCore.alg_order(alg::MER6v2) = 6
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OrdinaryDiffEqCore.alg_order(alg::RK6v4) = 6

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