Add tests

Author: visr

test/clock.jl

@@ -0,0 +1,38 @@
+using Test
+using SciMLBase
+using SciMLBase: Clock, PeriodicClock, Continuous, SolverStepClock, first_clock_tick_time,
+                 IndexedClock, canonicalize_indexed_clock
+
+@testset "Clock" begin
+    @test PeriodicClock(nothing, 0.2) isa TimeDomain
+    @test Continuous() isa TimeDomain
+    @test SolverStepClock() isa TimeDomain
+
+    @test Clock(1) isa TimeDomain
+    @test Clock(24.0; phase=0.1) == PeriodicClock(24.0, 0.1)
+    @test Clock(1//24) == PeriodicClock(1//24, 0.0)
+    @test Clock(;phase=0.2) == PeriodicClock(nothing, 0.2)
+
+    @test isclock(PeriodicClock(; dt=1.0))
+    @test !isclock(Continuous())
+    @test !isclock(SolverStepClock())
+
+    @test !issolverstepclock(PeriodicClock(; dt=1.0))
+    @test !issolverstepclock(Continuous())
+    @test issolverstepclock(SolverStepClock())
+
+    @test !iscontinuous(PeriodicClock(; dt=1.0))
+    @test iscontinuous(Continuous())
+    @test !iscontinuous(SolverStepClock())
+
+    @test is_discrete_time_domain(PeriodicClock(; dt=1.0))
+    @test !is_discrete_time_domain(Continuous())
+    @test is_discrete_time_domain(SolverStepClock())
+
+    @test first_clock_tick_time(PeriodicClock(; dt=2.0), 5.0) === 6.0
+    @test_throws ErrorException first_clock_tick_time(Continuous(), 5.0)
+    @test first_clock_tick_time(SolverStepClock(), 5.0) === 5.0
+
+    ic = Clock(1)[5]
+    @test ic === IndexedClock(Clock(1), 5)
+end

test/runtests.jl

@@ -66,6 +66,9 @@ end
         @time @safetestset "Initialization" begin
             include("initialization.jl")
         end
+        @time @safetestset "Clocks" begin
+            include("clock.jl")
+        end
     end
 
     if !is_APPVEYOR &&