Implementation of core blocks with central controller #43
Description
Blocks to be implemented
- Fetch
- Decode
- ROB
- Issue(s)
- Execution units
- Load buffer
- Store buffer
- Cache
- Main Memory
A block will have several phases to be simulated each clock, unlike the single simulate() in the v1.
Controller
This is in my opinion the hardest implementation decision. The requirement is to be flexible - add and mix blocks without restrictions. This rules out direct references between blocks. The implementations of blocks must be interchangeable. I think the way forward is interface per block type. Interfaces are implemented as a table of function pointers in Zig.
In terms of communication between blocks, there are:
- request/responses: get instruction at address 4
- (partial) flush after bad speculation
- 1:N communication: sending results from execution
It would be great to figure out a concept of a wire: it is similar to a mpmc channel or events.
The order of phases must be set, I cannot imagine how it could be defined in terms of dependencies.