Kernel/aarch64: Allow userspace to access CTR_EL0

CTR_EL0 is a read-only register that contains information about the
architecture of the caches. Both FreeBSD and Linux seem to allow direct
access to this register, so I don't think we should disallow EL0 to
access it.

This register is typically read during `__clear_cache()` to determine
the data/instruction cache line sizes and whether they are coherent.
`__clear_cache()` in turn is used by JITs to ensure that self-modifying
code works properly.

Author: spholz

Kernel/Arch/aarch64/Registers.h

@@ -819,6 +819,9 @@ struct alignas(u64) SCTLR_EL1 {
         system_control_register_el1.SA0 = 1;
         system_control_register_el1.IESB = 1;
 
+        // Allow EL0 to read CTR_EL0 (the cache type register).
+        system_control_register_el1.UCT = 1;
+
         // Fields that are RES1 if no extensions are supported:
         system_control_register_el1.ITD = 1;
         system_control_register_el1.SED = 1;