SiEPIC International Silicon Photonics Inverse Design competition series 2021

[lukasc-ubc]

What better way to spend your time during the Covid-19 pandemic, than participating in a physically-distanced design competition?

Goal: design and validate the world’s best integrated photonics 50/50 beam splitter

Ideal performance specifications for the final competition:

• Lossless four-port splitter with ratio: 50/50
• Fabrication insensitive: to within +/- 10nm thickness, +/- 10 nm width
• Broadband operation: entire S & C & L band (1460 to 1625 nm), or the entire O to U bands (1260 to 1675 nm)
• Polarization independent

There will be three design-fabricate-test cycles, with deadlines:

• February 8 2021 – run SiEPICfab-edX1
• Mid Summer 2021 – run SiEPICfab-edX2
• October 2021 – run SiEPICfab-edX3

There will be three competitions, each with increasing difficulty.

There will be three prizes, one for each round, of $500 each, sponsored by Ansys/Lumerical and CMC. Prize given only if permissible by law.

Winning candidates will be added to the SiEPIC-EBeam-PDK Library.

Design competition #1 – run SiEPICfab-edX1

Ideal performance specifications:

• Four port splitter with ratio: 50/50
• Fabrication insensitive: to within +/- 10nm thickness, +/- 10 nm width
• Broadband operation: entire S & C & L bands (1460 to 1625 nm)

Design competition #2 – run SiEPICfab-edX2

Ideal performance specifications:

• Four port splitter with ratio: 50/50
• Fabrication insensitive: to within +/- 10nm thickness, +/- 10 nm width
• Broadband operation: entire S & C & L bands (1460 to 1625 nm)
• Polarization independent
• Try to beat beam splitters by e.g. Thorlabs

Design competition #3 – run SiEPICfab-edX3

Ideal performance specifications:

• Four port splitter with ratio: 50/50
• Fabrication insensitive: to within +/- 10nm thickness, +/- 10 nm width
• Broadband operation: entire O to U bands (1260 to 1675 nm)
• Polarization independent

Fabrication constraints

• We are setting the minimum feature size to be 60 nm, which is compatible with the capabilities of non-phase-corrected immersion lithography available at leading 300 mm silicon photonics foundries. The devices will be fabricated using electron beam direct writing via SiEPICfab.
• The device maximum size is 50 µm in length, and 7 µm in height.
• Layouts are limited to multiple files each of 605x410 µm in size

Device ports:

• Port 1 and 2: inputs on the left side,
• Port 3 and 4: outputs on the right side
• Waveguide port geometry: strip waveguide (single etch), 220 nm height, designer’s choice for width

Figure of Merit and Evaluation calculation:

• Minimize the excess insertion loss, IL = - 10 log10(0.5) + 10 log10 (Port 3 / Port 1) for both polarizations across the wavelength range
• Minimize the imbalance in the splitting ratio, SR = abs(10 log10 (Port 3 / Port 2)), for injection in Port 1, for both polarizations across the wavelength range
• Figure of Merit (FOM) = max(IL-Simulated) + max(SR-Simulated), where max is the worst-case value across the measurement wavelength range and the worst-case for the two polarizations.

Submission requirement:

• A report describing your design. You may pursue a publication of work, in which case a draft version of your manuscript can be submitted as your report.
• Simulation results including a corner analysis to consider fabrication variations with process corners defined as ∆w = +/- 10 nm, and ∆h = +/- 10 nm, simulated over a specified wavelength range, for both TE and TM polarizations.
• Simulation files
• A compact model, which predicts the device response for any input to any output combination (e.g., input on Port 2, output on Port 1), for one or both polarizations (e.g,. Injection of both TE and TM light in Port 1). Can be in the form of an 8x8 S-Parameter wavelength-dependant model (4 ports, 2 polarizations)
• A calculation of the FOM defined above, using simulated data
• A layout submission to extract the performance parameters
• Experimental data analysis methodology, including plots overlaying simulations and experiments, and scripts (e.g. in Python)
• Optional: A compact model that is suitable for Monte Carlo simulations, namely the compact model should be parameterized (e.g., interpolation) within the process corners
• Presentation slides (submitted in PDF) of not more than 10 slides, summarizing your methodology, design, and results.
• Submit your entry to the following Dropbox link: xxx.
• By submitting an entry to this competition, you agree that you (or the organizer) will add the design and submitted files to the open-source SiEPIC-EBeam-PDK Library.

Experimental details:

• Fabrication coordinated by SiEPICfab, and carried out by UBC or Applied Nanotools
• Characterization coordinated by SiEPICfab, and carried out by UBC or EHVA Inc.

Register your intent to participate in the competition by introducing yourself in the SiEPIC-EBeam-PDK discussion forum.

Verification of contestant claims

• Taylor Robertson, Ansys-Lumerical

Judging

• Taylor Robertson, Ansys-Lumerical
• Mustafa Hammood, UBC and SiEPIC Kits
• Nicolas Jaeger, UBC
• Wei Shi, Laval University
• Jessica Zhang, CMC

Organizer

• Lukas Chrostowski, UBC

[chenshang2]

Hello, I am a Ph.D. student who works on photonics topology optimization, and I thought this competition is interesting and worth trying. What is the deadline for Design competition #2?

[lukasc-ubc]

Hi @chenshang2
We have paused the competition, and perhaps will resume it again one day.