Final update

[gnmsilveira]

Final update of my file

[lukasc-ubc]

You have a LOT of errors. Can you please fix?

ror: Disconnected pin: Disconnected pin
Error: Invalid Pin: Invalid pin found. Read more about requirements for components: https://github.com/SiEPIC/SiEPIC-Tools/wiki/Component-and-PCell-Layout
Error: Disconnected pin: Disconnected pin
Error: Invalid Pin: Invalid pin found. Read more about requirements for components: https://github.com/SiEPIC/SiEPIC-Tools/wiki/Component-and-PCell-Layout
Error: Disconnected pin: Disconnected pin
Error: Invalid Pin: Invalid pin found. Read more about requirements for components: https://github.com/SiEPIC/SiEPIC-Tools/wiki/Component-and-PCell-Layout
Error: Disconnected pin: Disconnected pin
Error: Invalid Pin: Invalid pin found. Read more about requirements for components: https://github.com/SiEPIC/SiEPIC-Tools/wiki/Component-and-PCell-Layout
Error: Disconnected pin: Disconnected pin
Error: Invalid Pin: Invalid pin found. Read more about requirements for components: https://github.com/SiEPIC/SiEPIC-Tools/wiki/Component-and-PCell-Layout
Error: Disconnected pin: Disconnected pin
Error: Disconnected pin: Disconnected pin
Error: Disconnected pin: Disconnected pin
Error: Invalid Pin: Invalid pin found. Read more about requirements for components: https://github.com/SiEPIC/SiEPIC-Tools/wiki/Component-and-PCell-Layout
Error: Invalid Pin: Invalid pin found. Read more about requirements for components: https://github.com/SiEPIC/SiEPIC-Tools/wiki/Component-and-PCell-Layout
Error: Disconnected pin: Disconnected pin
Error: Invalid Pin: Invalid pin found. Read more about requirements for components: https://github.com/SiEPIC/SiEPIC-Tools/wiki/Component-and-PCell-Layout
Error: Disconnected pin: Disconnected pin
Error: Invalid Pin: Invalid pin found. Read more about requirements for components: https://github.com/SiEPIC/SiEPIC-Tools/wiki/Component-and-PCell-Layout
Error: Disconnected pin: Disconnected pin
Error: Invalid Pin: Invalid pin found. Read more about requirements for components: https://github.com/SiEPIC/SiEPIC-Tools/wiki/Component-and-PCell-Layout
Error: Disconnected pin: Disconnected pin
Error: Invalid Pin: Invalid pin found. Read more about requirements for components: https://github.com/SiEPIC/SiEPIC-Tools/wiki/Component-and-PCell-Layout
Error: Disconnected pin: Disconnected pin
Error: Disconnected pin: Disconnected pin
Error: Invalid Pin: Invalid pin found. Read more about requirements for components: https://github.com/SiEPIC/SiEPIC-Tools/wiki/Component-and-PCell-Layout
Error: Invalid Pin: Invalid pin found. Read more about requirements for components: https://github.com/SiEPIC/SiEPIC-Tools/wiki/Component-and-PCell-Layout
Error: Disconnected pin: Disconnected pin
Error: Invalid Pin: Invalid pin found. Read more about requirements for components: https://github.com/SiEPIC/SiEPIC-Tools/wiki/Component-and-PCell-Layout
Error: Disconnected pin: Disconnected pin
Error: Invalid Pin: Invalid pin found. Read more about requirements for components: https://github.com/SiEPIC/SiEPIC-Tools/wiki/Component-and-PCell-Layout
Error: Disconnected pin: Disconnected pin
Error: Invalid Pin: Invalid pin found. Read more about requirements for components: https://github.com/SiEPIC/SiEPIC-Tools/wiki/Component-and-PCell-Layout
Error: Disconnected pin: Disconnected pin
Error: Invalid Pin: Invalid pin found. Read more about requirements for components: https://github.com/SiEPIC/SiEPIC-Tools/wiki/Component-and-PCell-Layout
Error: Disconnected pin: Disconnected pin
Error: Disconnected pin: Disconnected pin

• Previous label: (' SiEPIC-Tools verification: 370 errors\n 2025-10-11 01:35:33\n SiEPIC-Tools v0.5.31\n technology: EBeam - v0.4.53\n win32\n Python: 3.11.6 (main, Oct 3 2023, 09:12:56) [GCC 13.2.0 64 bit (AMD64)], C:\Users\Gilliard\AppData\Roaming\KLayout\pymod\n KLayout v0.30.4\n',r0 9821310,10115930) s=100
  KLayout SiEPIC-Tools version 0.5.31
  SiEPIC-Tools is up to date (0.5.31 vs 0.5.31).
  Version check, time: 0.032073259353637695 seconds
  1312
  Errors detected: EBeam_gilliardn_v2.gds, 1312 errors.

[gnmsilveira]

Sorry, I thought it wasn't mandatory to include the pins. I thIs there still time to submit a corrected version?

[lukasc-ubc]

Yes, please submit by tonight (in 3.5 hours). Yes, passing verification is a requirement.

[github-actions]

This fabrication run is closed. Please submit your design in the next fabrication run. https://github.com/SiEPIC/openEBL-2026-02

[lukasc-ubc]

This is an experimental feature. The goal is to run a circuit simulation on the design, and return the results for human verification.

❌ Simulation failed for EBeam_gilliardn_v2.gds (exit code 1)

stdout:

Warning: In file /home/lukasc/simulations/gnmsilveira/EBeam_gilliardn_v2.gds:
Warning: Record length larger than 0x8000 encountered: interpreting as unsigned (position=935330, record number=5745, cell=bragg1$2$1)
Warning: Record length larger than 0x8000 encountered: interpreting as unsigned (position=976722, record number=5750, cell=bragg1$2$1)
Warning: Record length larger than 0x8000 encountered: interpreting as unsigned (position=1046744, record number=6268, cell=bragg1$2)
Warning: Record length larger than 0x8000 encountered: interpreting as unsigned (position=1088136, record number=6273, cell=bragg1$2)
Warning: Record length larger than 0x8000 encountered: interpreting as unsigned (position=1129690, record number=6296, cell=bragg1)
Warning: Record length larger than 0x8000 encountered: interpreting as unsigned (position=1171082, record number=6301, cell=bragg1)
Warning: Record length larger than 0x8000 encountered: interpreting as unsigned (position=1230336, record number=6710, cell=bragg1$2$2)
Warning: Record length larger than 0x8000 encountered: interpreting as unsigned (position=1271728, record number=6715, cell=bragg1$2$2)
KLayout SiEPIC-Tools version 0.5.29
New version of SiEPIC-Tools is available (0.5.31 vs 0.5.29).
Version check, time: 0.20985054969787598 seconds
SiEPIC-EBeam-PDK Python module: siepic_ebeam_pdk, KLayout technology: EBeam
SiEPIC-EBeam-PDK Python module: pymacros, v0.4.50
Libraries associated with Technology EBeam: ['EBeam', 'EBeam-ANT', 'EBeam-Dream', 'EBeam-SiN', 'EBeam_Beta']
PDK folder: /home/lukasc/.local/lib/python3.10/site-packages/siepic_ebeam_pdk/__init__.py
multiple top cells: 
bragg1$2$2
bend_euler_R10_A90_P0p5_a3fd587b$1$1$1
straight_L20p7_CSstrip_W0p5_N2$1$1$1
component2_1$1$1
straight_L47p32_CSstrip_W0p4_N2$1$1
bend_euler_R10_A90_P0p5_1e25b3b4$1$1
bend_euler_R10_Am90_P0p_2da4d05b$1$1
taper_L9p84000000000000_4a3bdda8$1$1
gilliardn_v2

📸 Simulation result image(s):

To re-run this simulation, please make a change to the layout file (simply running V verification will change the date stamp in the layout), save it, and upload it to your GitHub fork. This will trigger this simulation to run again.

I hereby grant you permission to use these plots for inclusion in a course report.

• Simulation date: 2025-10-12 07:57:30 PDT

[lukasc-ubc]

you design has many top cells. I will merge and delete the extra.

[lukasc-ubc]

I'm sorry, but your design won't work. You have modified the Black box grating coupler cells, which prevents us from automatically replacing them. The layout needs to keep the original cells intact, e.g., GC_TE_1550_8degOxide_BB

[gnmsilveira]

I apologize for my mistake. Thank you very much for trying! Em domingo, 12 de outubro de 2025 às 14:08:31 BRT, Lukas Chrostowski ***@***.***> escreveu: lukasc-ubc left a comment (SiEPIC/openEBL-2025-10#262) I'm sorry, but your design won't work. You have modified the Black box grating coupler cells, which prevents us from automatically replacing them. The layout needs to keep the original cells intact, e.g., GC_TE_1550_8degOxide_BB — Reply to this email directly, view it on GitHub, or unsubscribe. You are receiving this because you authored the thread.Message ID: ***@***.***>