Final Submission

[DashCodeHub]

Removed component from old PDK file

[DashCodeHub]

@lukasc-ubc , Thank you Dr. Lukas. IPKISS indeed had the old pdk. I rectified and removed the old compoenents and used the new ones.

[lukasc-ubc]

This is an experimental feature. The goal is to run a circuit simulation on the design, and return the results for human verification.

✅ Simulation results for EBeam_priyabrata_52.gds

stdout:

KLayout SiEPIC-Tools version 0.5.29
New version of SiEPIC-Tools is available (0.5.31 vs 0.5.29).
Version check, time: 0.21301031112670898 seconds
SiEPIC-EBeam-PDK Python module: siepic_ebeam_pdk, KLayout technology: EBeam
SiEPIC-EBeam-PDK Python module: pymacros, v0.4.50
Libraries associated with Technology EBeam: ['EBeam', 'EBeam-ANT', 'EBeam-Dream', 'EBeam-SiN', 'EBeam_Beta']
PDK folder: /home/lukasc/.local/lib/python3.10/site-packages/siepic_ebeam_pdk/__init__.py

Found 6 opt-in labels: ['opt_in_TE_1550_device_priyabrata_52_RX1', 'opt_in_TE_1550_device_priyabrata_52_RX2', 'opt_in_TE_1550_device_priyabrata_52_RX3', 'opt_in_TE_1550_device_priyabrata_52_RX4', 'opt_in_TE_1550_device_priyabrata_52_RX5', 'opt_in_TE_1550_device_priyabrata_52_RX6']

Running simulation for opt_in_TE_1550_device_priyabrata_52_RX1
Design for Test rules from PDK: /home/lukasc/.local/lib/python3.10/site-packages/siepic_ebeam_pdk/DFT.xml
No simulation results available for input 1 for opt_in_TE_1550_device_priyabrata_52_RX1
No simulation results available for input 2 for opt_in_TE_1550_device_priyabrata_52_RX1
No simulation results available for input 3 for opt_in_TE_1550_device_priyabrata_52_RX1
  skipping circuit.

Running simulation for opt_in_TE_1550_device_priyabrata_52_RX2
Design for Test rules from PDK: /home/lukasc/.local/lib/python3.10/site-packages/siepic_ebeam_pdk/DFT.xml
No simulation results available for input 1 for opt_in_TE_1550_device_priyabrata_52_RX2
No simulation results available for input 2 for opt_in_TE_1550_device_priyabrata_52_RX2
No simulation results available for input 3 for opt_in_TE_1550_device_priyabrata_52_RX2
  skipping circuit.

Running simulation for opt_in_TE_1550_device_priyabrata_52_RX3
Design for Test rules from PDK: /home/lukasc/.local/lib/python3.10/site-packages/siepic_ebeam_pdk/DFT.xml
No simulation results available for input 1 for opt_in_TE_1550_device_priyabrata_52_RX3
No simulation results available for input 2 for opt_in_TE_1550_device_priyabrata_52_RX3
No simulation results available for input 3 for opt_in_TE_1550_device_priyabrata_52_RX3
  skipping circuit.

Running simulation for opt_in_TE_1550_device_priyabrata_52_RX4
Design for Test rules from PDK: /home/lukasc/.local/lib/python3.10/site-packages/siepic_ebeam_pdk/DFT.xml
No simulation results available for input 1 for opt_in_TE_1550_device_priyabrata_52_RX4
No simulation results available for input 2 for opt_in_TE_1550_device_priyabrata_52_RX4
No simulation results available for input 3 for opt_in_TE_1550_device_priyabrata_52_RX4
  skipping circuit.

Running simulation for opt_in_TE_1550_device_priyabrata_52_RX5
Design for Test rules from PDK: /home/lukasc/.local/lib/python3.10/site-packages/siepic_ebeam_pdk/DFT.xml
No simulation results available for input 1 for opt_in_TE_1550_device_priyabrata_52_RX5
No simulation results available for input 2 for opt_in_TE_1550_device_priyabrata_52_RX5
No simulation results available for input 3 for opt_in_TE_1550_device_priyabrata_52_RX5
  skipping circuit.

Running simulation for opt_in_TE_1550_device_priyabrata_52_RX6
Design for Test rules from PDK: /home/lukasc/.local/lib/python3.10/site-packages/siepic_ebeam_pdk/DFT.xml
No simulation results available for input 1 for opt_in_TE_1550_device_priyabrata_52_RX6
No simulation results available for input 2 for opt_in_TE_1550_device_priyabrata_52_RX6
No simulation results available for input 3 for opt_in_TE_1550_device_priyabrata_52_RX6
  skipping circuit.
done in 0:00:33.7

📸 Simulation result image(s):

To re-run this simulation, please make a change to the layout file (simply running V verification will change the date stamp in the layout), save it, and upload it to your GitHub fork. This will trigger this simulation to run again.

I hereby grant you permission to use these plots for inclusion in a course report.

• Simulation date: 2025-10-11 21:45:23 PDT

[lukasc-ubc]

Interesting layouts. Do you have models for each of the cells? Interesting way of breaking it up.
Did you simulate the circuit?

[DashCodeHub]

Yes Dr. Lukas, I do have the models for the components but the up and the down part of the ring both as merged together. I tried other ways but, for SiEPIC PDK only horizontal flipped compoents when joined with each other show no invalid port error in KLayout when verified.

This circuit (forgot to chnage the orientation of the GCs) is what I was intending to design and submit (which I finished now) but, I was too tangled up with KLayout Errors hence, and had to work on PDK level on IPKISS to understand the designs and create the above sub-components. Hopefully I can submit the entire design next time.