Skip to content

Add files via upload#335

Merged
MateoBCalles merged 2 commits intoSiEPIC:mainfrom
BiCinur:main
Oct 12, 2025
Merged

Add files via upload#335
MateoBCalles merged 2 commits intoSiEPIC:mainfrom
BiCinur:main

Conversation

@BiCinur
Copy link
Contributor

@BiCinur BiCinur commented Oct 12, 2025

Sorry for the delay. I'm still working on it to make a single frequency and high SMRR. I have to add appodization as well. This one contains the quarter wavelength phase delay in the middle between two Bragg sections.

Sorry for the delay. I'm still working on it to make a single frequency and high SMRR. I have to add appodization as well. This one contains the quarter wavelength phase delay in the middle between two Bragg sections.
@github-actions
Copy link
Contributor

Welcome, new contributor!

Thank you for uploading your design.

If you have not already checked it, please run the SiEPIC Functional Verification in KLayout, using the menu SiEPIC-Verification-Functional Layout Check (V).

We are using GitHub Actions to perform several automated checks. Please ensure that there are no failing checks. Each time you update the files in your fork, this pull request will trigger the automated verification. Check back in a few minutes once they are complete. Click on any failing check indiciated with a red "X" to see the detailed errors.

You may continue making updates to your design, or even contributing additonal designs (using a separate file name), until the tape-out deadline.

@BiCinur
Copy link
Contributor Author

BiCinur commented Oct 12, 2025

Can I work on this for a few more hours? I need to add appodization to it.

@lukasc-ubc
Copy link
Member

lukasc-ubc commented Oct 12, 2025

This is an experimental feature. The goal is to run a circuit simulation on the design, and return the results for human verification.

✅ Simulation results for ELEC413_Jamal.gds

stdout:

KLayout SiEPIC-Tools version 0.5.29
New version of SiEPIC-Tools is available (0.5.31 vs 0.5.29).
Version check, time: 0.17321062088012695 seconds
SiEPIC-EBeam-PDK Python module: siepic_ebeam_pdk, KLayout technology: EBeam
SiEPIC-EBeam-PDK Python module: pymacros, v0.4.50
Libraries associated with Technology EBeam: ['EBeam', 'EBeam-ANT', 'EBeam-Dream', 'EBeam-SiN', 'EBeam_Beta']
PDK folder: /home/lukasc/.local/lib/python3.10/site-packages/siepic_ebeam_pdk/__init__.py

Found 2 opt-in labels: ['opt_in_TE_1550_BraggSweepN950_per317nm_w500nm_dW20nm_PS', 'opt_in_TE_1550_BraggSweepN950_per317nm_w500nm_dW80nm_PS']

Running simulation for opt_in_TE_1550_BraggSweepN950_per317nm_w500nm_dW20nm_PS
Design for Test rules from PDK: /home/lukasc/.local/lib/python3.10/site-packages/siepic_ebeam_pdk/DFT.xml
Simulation completed for opt_in_TE_1550_BraggSweepN950_per317nm_w500nm_dW20nm_PS.

Running simulation for opt_in_TE_1550_BraggSweepN950_per317nm_w500nm_dW80nm_PS
Design for Test rules from PDK: /home/lukasc/.local/lib/python3.10/site-packages/siepic_ebeam_pdk/DFT.xml
Simulation completed for opt_in_TE_1550_BraggSweepN950_per317nm_w500nm_dW80nm_PS.
done in 0:00:18.7

📸 Simulation result image(s):
ELEC413_Jamal.png
ELEC413_Jamal_opt_in_te_1550_braggsweepn950_per317nm_w500nm_dw20nm_ps_l.png
ELEC413_Jamal_opt_in_te_1550_braggsweepn950_per317nm_w500nm_dw80nm_ps_l.png

To re-run this simulation, please make a change to the layout file (simply running V verification will change the date stamp in the layout), save it, and upload it to your GitHub fork. This will trigger this simulation to run again.

I hereby grant you permission to use these plots for inclusion in a course report.

  • Simulation date: 2025-10-12 00:19:24 PDT

@MateoBCalles MateoBCalles merged commit a1b9435 into SiEPIC:main Oct 12, 2025
5 checks passed
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

Projects

None yet

Development

Successfully merging this pull request may close these issues.

3 participants