WDC 65C02 cycle count seems incorrect for opcode $5C

[sidneycadot]

Hi,

I've implemented instruction-level clock cycle tests that runs on hardware as a reference.

For the 65C02, I use a Neo6502 board, which has a WDC W65C02S6TQG-14 processor.

I have firmly established that an opcode $5c (supposedly a NOP with some odd kind of absolute addressing) on that CPU takes 8 clock cycles. This confirms some sources to be found on the web (eg http://www.6502.org/tutorials/65c02opcodes.html, section 9).

However, the 65x02 testsuite lists this opcode with 4 clock cycles (https://raw.githubusercontent.com/SingleStepTests/65x02/refs/heads/main/wdc65c02/v1/5c.json). This seems to be incorrect.

[BulbulatorMacher]

According to the https://laughtonelectronics.com/Arcana/KimKlone/Kimklone_opcode_mapping.html, 5C 1234h ($5c $34 $12) takes 3 cycles to fetch the instruction and then it reads $ff34 once and four times $ffff