update new

Author: vickiegpt

include/cxlcounter.h

@@ -14,9 +14,7 @@
 
 #include <cstdint>
 #include <map>
-#include <string>
 #include <tuple>
-#include <unordered_map>
 #include <vector>
 
 /** TODO: Whether to using the pebs to record the state. add back invalidation migrate huge/ page and prefetch*/

include/cxlendpoint.h

@@ -19,14 +19,14 @@
 #include <map>
 #include <string>
 #include <tuple>
-#include <unordered_map>
+#include <unordered_set>
 #include <vector>
 #define ROB_SIZE 512
 
 struct occupation_info {
-    uint64_t timestamp;
-    uint64_t address;
-    uint64_t access_count;
+    uint64_t timestamp{};
+    uint64_t address{};
+    uint64_t access_count{};
 };
 struct rob_info {
     std::map<int, int64_t> m_bandwidth, m_count;
@@ -62,6 +62,8 @@ class CXLMemExpander : public CXLEndPoint {
     uint64_t capacity;
 
     std::vector<occupation_info> occupation; // timestamp, pa
+    std::unordered_set<uint64_t> address_cache{};
+    bool cache_valid = false;
     CXLMemExpanderEvent counter{};
     CXLMemExpanderEvent last_counter{};
     mutable std::shared_mutex occupationMutex_; // 使用共享互斥锁允许多个读取者
@@ -82,6 +84,28 @@ class CXLMemExpander : public CXLEndPoint {
                              double dramlatency) override; // traverse the tree to calculate the latency
     double calculate_bandwidth(const std::vector<std::tuple<uint64_t, uint64_t>> &elem) override;
     void delete_entry(uint64_t addr, uint64_t length) override;
+    void update_address_cache() {
+        if (cache_valid) return;
+
+        address_cache.clear();
+        for (const auto& occ : occupation) {
+            address_cache.insert(occ.address);
+        }
+        cache_valid = true;
+    }
+    // 当 occupation 更新时调用此函数
+    void invalidate_cache() {
+        cache_valid = false;
+    }
+
+    // 检查地址是否在 occupation 中
+    bool is_address_local(uint64_t addr) {
+        if (!cache_valid) {
+            update_address_cache();
+        }
+
+        return address_cache.find(addr) != address_cache.end();
+    }
 };
 class CXLSwitch : public CXLEndPoint {
 public:

include/perf.h

@@ -26,7 +26,6 @@
 #include <sys/ioctl.h>
 #include <sys/syscall.h>
 #include <sys/types.h>
-#include <thread>
 #include <tuple>
 #include <unistd.h>
 

microbench/st_serial.cpp

@@ -0,0 +1,119 @@
+/*
+ * Microbench testies for MLP and memory latency in CXLMS
+ *
+ *  By: Andrew Quinn
+ *      Yiwei Yang
+ *
+ *  Copyright 2023 Regents of the Univeristy of California
+ *  UC Santa Cruz Sluglab.
+ */
+
+
+#include <errno.h>
+#include <stdio.h>
+#include <assert.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <cpuid.h>
+#include <pthread.h>
+#include <stdlib.h>
+
+#include <sys/mman.h>
+
+
+#define STR_HELPER(x) #x
+#define STR(x) STR_HELPER(x)
+
+#define MOVE_SIZE 128
+#define MAP_SIZE  (long)(1024 * 1024 * 1024)
+#define CACHELINE_SIZE  64
+
+#ifndef FENCE_COUNT
+#define FENCE_COUNT 8
+#endif
+
+#define FENCE_BOUND (FENCE_COUNT * MOVE_SIZE)
+
+// we need to jump in MOVE_SIZE increments otherwise segfault!
+
+#define BODY(start)						\
+  "xor %%r8, %%r8 \n"						\
+  "pxor %%xmm1, %%xmm1 \n"					\
+  "LOOP_START%=: \n"						\
+  "lea (%[" #start "], %%r8), %%r9 \n"				\
+  "movdqa  %%xmm1, (%%r9) \n"					\
+  "add $" STR(MOVE_SIZE) ", %%r8 \n"				\
+  "cmp $" STR(FENCE_BOUND) ",%%r8\n"				\
+  "mfence \n" \
+  "jl LOOP_START%= \n"
+
+
+int main(int argc, char **argv) {
+
+  // in principle, you would want to clear out cache lines (and the
+  // pipeline) before doing any of the inline assembly stuff.  But,
+  // that's hard.  And, its probably noise when you execute over
+  // enough things.
+
+
+  // allocate some meomery
+  char *base =(char *) mmap(nullptr,
+		    MAP_SIZE,
+		    PROT_READ | PROT_WRITE,
+		    MAP_ANONYMOUS | MAP_PRIVATE,
+		    -1,
+		    0);
+
+  if (base == MAP_FAILED) {
+    fprintf(stderr, "oops, you suck %d\n", errno);
+    return -1;
+  }
+  char *addr = NULL;
+
+  intptr_t *iaddr = (intptr_t*) base;
+  intptr_t hash = 0;
+  struct timespec tstart = {0,0}, tend = {0,0};
+
+  // Necessary so that we don't include allocation costs in our benchmark
+  while (iaddr < (intptr_t *)(base + MAP_SIZE)) {
+    hash = hash ^ (intptr_t) iaddr;
+    *iaddr = hash;
+    iaddr++;
+  }
+
+  // should flush everything from the cache. But, how big is the cache?
+  addr = base;
+  while (addr < (base + MAP_SIZE)) {
+    asm volatile(
+		 "mov %[buf], %%rsi\n"
+		 "clflush (%%rsi)\n"
+		 :
+		 : [buf] "r" (addr)
+		 : "rsi");
+    addr += CACHELINE_SIZE;
+  }
+
+  asm volatile ("mfence\n" :::);
+
+  clock_gettime(CLOCK_MONOTONIC, &tstart);
+  addr = base;
+  while (addr < (base + MAP_SIZE)) {
+    //fprintf (stderr, "addr %p bound %p\n", addr, base + MAP_SIZE);
+    asm volatile(
+		 BODY(addr)
+		 :
+		 : [addr] "r" (addr)
+		 : "r8", "r9", "xmm0");
+
+      addr += (FENCE_COUNT * MOVE_SIZE);
+  }
+  clock_gettime(CLOCK_MONOTONIC, &tend);
+  uint64_t nanos = (1000000000  * tend.tv_sec + tend.tv_nsec);
+  nanos -= (1000000000 * tstart.tv_sec + tstart.tv_nsec);
+
+
+  printf("%lu\n", nanos);
+  return 0;
+}
+

src/cxlcontroller.cpp

@@ -103,6 +103,10 @@ void CXLController::insert_one(thread_info &t_info, lbr &lbr) {
     ring_buffer.push(lbr);
 
     for (int i = 0; i < llcm_count; i++) {
+        if (t_info.llcm_type.empty()) {
+            // 如果 llcm_type 为空，直接插入 0
+            t_info.llcm_type.push(0);
+        }
         rob.m_count[t_info.llcm_type.front()]++;
         t_info.llcm_type_rob.push(t_info.llcm_type.front());
         t_info.llcm_type.pop();