@@ -193,18 +193,53 @@ const char* cxl_backend_type_name(cxl_backend_type_t type);
193193#define CXL_SHM_CACHELINE_SIZE 64
194194
195195/* Request types */
196- #define CXL_SHM_REQ_NONE 0
197- #define CXL_SHM_REQ_READ 1
198- #define CXL_SHM_REQ_WRITE 2
199- #define CXL_SHM_REQ_ATOMIC_FAA 3
200- #define CXL_SHM_REQ_ATOMIC_CAS 4
201- #define CXL_SHM_REQ_FENCE 5
196+ #define CXL_SHM_REQ_NONE 0
197+ #define CXL_SHM_REQ_READ 1
198+ #define CXL_SHM_REQ_WRITE 2
199+ #define CXL_SHM_REQ_ATOMIC_FAA 3
200+ #define CXL_SHM_REQ_ATOMIC_CAS 4
201+ #define CXL_SHM_REQ_FENCE 5
202+ #define CXL_SHM_REQ_READ_META 6 /* Read with metadata */
203+ #define CXL_SHM_REQ_WRITE_META 7 /* Write with metadata */
204+ #define CXL_SHM_REQ_GET_META 8 /* Get metadata only */
205+ #define CXL_SHM_REQ_SET_META 9 /* Set metadata only */
202206
203207/* Response status */
204208#define CXL_SHM_RESP_NONE 0
205209#define CXL_SHM_RESP_OK 1
206210#define CXL_SHM_RESP_ERROR 2
207211
212+ /* MESI Cache States */
213+ #define CXL_CACHE_INVALID 0
214+ #define CXL_CACHE_SHARED 1
215+ #define CXL_CACHE_EXCLUSIVE 2
216+ #define CXL_CACHE_MODIFIED 3
217+
218+ /* Metadata flags */
219+ #define CXL_META_FLAG_DIRTY 0x01
220+ #define CXL_META_FLAG_LOCKED 0x02
221+ #define CXL_META_FLAG_PINNED 0x04
222+
223+ /* Cacheline metadata structure (64 bytes) - compatible with Splash libpgas */
224+ typedef struct {
225+ uint8_t cache_state ; /* MESI state */
226+ uint8_t owner_id ; /* Current owner host/thread ID */
227+ uint16_t sharers_bitmap ; /* Bitmap of hosts/threads sharing this line */
228+ uint32_t access_count ; /* Number of accesses */
229+ uint64_t last_access_time ; /* Timestamp of last access */
230+ uint64_t virtual_addr ; /* Virtual address mapping */
231+ uint64_t physical_addr ; /* Physical address */
232+ uint32_t version ; /* Version number for coherency */
233+ uint8_t flags ; /* Various flags (dirty, locked, etc.) */
234+ uint8_t reserved [23 ]; /* Reserved for future use */
235+ } __attribute__((packed )) cxl_cacheline_metadata_t ;
236+
237+ /* PGAS Memory Entry: 128 bytes (64 data + 64 metadata) per cacheline */
238+ typedef struct {
239+ uint8_t data [CXL_SHM_CACHELINE_SIZE ]; /* 64 bytes of data */
240+ cxl_cacheline_metadata_t metadata ; /* 64 bytes of metadata */
241+ } __attribute__((packed , aligned (128 ))) cxl_pgas_entry_t ;
242+
208243/* Shared memory slot for request/response */
209244typedef struct {
210245 volatile uint32_t req_type ; /* Request type */
@@ -215,23 +250,29 @@ typedef struct {
215250 volatile uint64_t expected ; /* Expected value for CAS */
216251 volatile uint64_t latency_ns ; /* Simulated latency */
217252 volatile uint64_t timestamp ; /* Request timestamp */
218- uint8_t data [CXL_SHM_CACHELINE_SIZE ]; /* Data buffer */
219- uint8_t padding [ 64 - 8 ] ; /* Align to 128 bytes */
220- } __attribute__((aligned (128 ))) cxl_shm_slot_t ;
253+ uint8_t data [CXL_SHM_CACHELINE_SIZE ]; /* Data buffer (64 bytes) */
254+ cxl_cacheline_metadata_t metadata ; /* Metadata buffer (64 bytes) */
255+ } __attribute__((aligned (256 ))) cxl_shm_slot_t ;
221256
222257/* Shared memory header */
223258typedef struct {
224259 uint64_t magic ; /* Magic number for validation */
225260 uint32_t version ; /* Protocol version */
226261 uint32_t num_slots ; /* Number of request slots */
227262 volatile uint32_t server_ready ; /* Server is ready flag */
228- uint32_t reserved ;
263+ uint32_t flags ; /* Header flags */
229264 uint64_t memory_base ; /* Base address of simulated memory */
230265 uint64_t memory_size ; /* Size of simulated memory */
231- uint8_t padding [64 - 40 ]; /* Pad header to 64 bytes */
266+ uint64_t num_cachelines ; /* Number of cachelines (memory_size/64) */
267+ uint32_t metadata_enabled ; /* 1 if metadata transfer is enabled */
268+ uint32_t entry_size ; /* Size of each entry (64 or 128 bytes) */
269+ uint8_t padding [64 - 56 ]; /* Pad header to 64 bytes */
232270 cxl_shm_slot_t slots []; /* Request/response slots */
233271} __attribute__((aligned (64 ))) cxl_shm_header_t ;
234272
273+ /* Header flags */
274+ #define CXL_SHM_FLAG_METADATA_ENABLED 0x01
275+
235276/* Size calculation */
236277#define CXL_SHM_HEADER_SIZE (nslots ) \
237278 (sizeof(cxl_shm_header_t) + (nslots) * sizeof(cxl_shm_slot_t))
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