Inconsistencies with User Guide or SDK

[MelonShooter]

This is a tracking issue for any inconsistencies we find with what should be done and the SDK and user guide. After the competition is over, we can report these to Analog Devices.

[Flaneur3434]

The User Guide does not mention the need to disable and enable the icc0 before and after a flash write operation. The MSDK mentions the need to disable the icc0 in a comment here, flc_common.c#L62. The details on how to disable and enable the icc0 are found here icc_reva.c#L76 and here icc_reva.c#L63 respectively.

There are multiple step that need to be executed after a non-read flash operation the User Guide never mentions. The MSDK details the operations in flc_me17.c.

User guide does not describe the procedure necessary to protect flash page reads and writes. The MSDK details the operations in flc_reva.c.

[MelonShooter]

For UART, in page 43 of the MAX78000 datasheet (not MAX78000FTHR datasheet), it's stated that the hardware flow control (HFC) is available solely for UART0 while page 170 of the user guide states that HFC is available on UART0-UART2 and not UART3. The datasheet is likely right in this case considering there are no alternate function pins for CTS and RTS for UART1-3 and the uart_ai85.c file used in the SDK for our board shows that only UART0 has these pins.

In the same tables on those pages, it's stated that UART0-UART2 function in LPM on the datasheet while in the user guide, it does not. It's unknown at this point what's right but this doesn't matter too much for us at this point

[dpleshkov]

For WDT, in page 335 of the user guide, it states to wait until WDTn_CTRL.clkrdy is set to 1 when disabling/enabling the peripheral clock. This, however, is not being done in the MSDK, and in practice clkrdy never seems to go to 1 when polling.

Additionally, the MSDK uses different feed sequence codes than stated in the user guide. The user guide states to use 0xA5, then 0x5A as the feed sequence for all three operations: kick, disable, and enable. However, the MSDK uses 0xDE, 0xAD to disable and 0xFE, 0xED to enable, using the stated 0xA5, 0x5A only to kick, i.e., reset the timer. In practice, using the stated 0xA5, 0x5A operations appears to work fine for all three operations.

[190n]

Page 92 of the user guide says to write 1 to the bit GCR_RST1.cpu1 to reset the RISC-V core, but the field is marked as read-only in the "Access" column as well as in the SVD.