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harisokanovicjnettlet
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tpm_tis: fix stall after iowrite*()s
ioread8() operations to TPM MMIO addresses can stall the cpu when immediately following a sequence of iowrite*()'s to the same region. For example, cyclitest measures ~400us latency spikes when a non-RT usermode application communicates with an SPI-based TPM chip (Intel Atom E3940 system, PREEMPT_RT_FULL kernel). The spikes are caused by a stalling ioread8() operation following a sequence of 30+ iowrite8()s to the same address. I believe this happens because the write sequence is buffered (in cpu or somewhere along the bus), and gets flushed on the first LOAD instruction (ioread*()) that follows. The enclosed change appears to fix this issue: read the TPM chip's access register (status code) after every iowrite*() operation to amortize the cost of flushing data to chip across multiple instructions. Signed-off-by: Haris Okanovic <[email protected]> Signed-off-by: Sebastian Andrzej Siewior <[email protected]> Signed-off-by: Steven Rostedt (VMware) <[email protected]>
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drivers/char/tpm/tpm_tis.c

Lines changed: 27 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -50,6 +50,31 @@ static inline struct tpm_tis_tcg_phy *to_tpm_tis_tcg_phy(struct tpm_tis_data *da
5050
return container_of(data, struct tpm_tis_tcg_phy, priv);
5151
}
5252

53+
#ifdef CONFIG_PREEMPT_RT_FULL
54+
/*
55+
* Flushes previous write operations to chip so that a subsequent
56+
* ioread*()s won't stall a cpu.
57+
*/
58+
static inline void tpm_tis_flush(void __iomem *iobase)
59+
{
60+
ioread8(iobase + TPM_ACCESS(0));
61+
}
62+
#else
63+
#define tpm_tis_flush(iobase) do { } while (0)
64+
#endif
65+
66+
static inline void tpm_tis_iowrite8(u8 b, void __iomem *iobase, u32 addr)
67+
{
68+
iowrite8(b, iobase + addr);
69+
tpm_tis_flush(iobase);
70+
}
71+
72+
static inline void tpm_tis_iowrite32(u32 b, void __iomem *iobase, u32 addr)
73+
{
74+
iowrite32(b, iobase + addr);
75+
tpm_tis_flush(iobase);
76+
}
77+
5378
static bool interrupts = true;
5479
module_param(interrupts, bool, 0444);
5580
MODULE_PARM_DESC(interrupts, "Enable interrupts");
@@ -103,7 +128,7 @@ static int tpm_tcg_write_bytes(struct tpm_tis_data *data, u32 addr, u16 len,
103128
struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data);
104129

105130
while (len--)
106-
iowrite8(*value++, phy->iobase + addr);
131+
tpm_tis_iowrite8(*value++, phy->iobase, addr);
107132
return 0;
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}
109134

@@ -127,7 +152,7 @@ static int tpm_tcg_write32(struct tpm_tis_data *data, u32 addr, u32 value)
127152
{
128153
struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data);
129154

130-
iowrite32(value, phy->iobase + addr);
155+
tpm_tis_iowrite32(value, phy->iobase, addr);
131156
return 0;
132157
}
133158

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