Interrupt handle problem when debug

[HaroldZ32]

Hi,

There's a problem when I try to debug with nax.

If an interrupt occurs while cpu is halted, it should be holded.

And if there's an EXECUTE request from Debug Module, the pipeline will run for one step, but it will trigger the isFireing signal of decoded stage of Frontend pipeline. And the interrupt will be handled by mistake.

In risc-v debug spec, all the interrupt should be masked.

1.0 Version

0.13 Version

The result is the MIE register will be pulled down, if there's no program to write it for this problem. And the interrupt will not be handled forever.

I think it's a bug that should be fixed. I'll make a PR if you think it's definitely a problem.
Thank for you help!

[Dolu1990]

Hi,

Looking at the code, seems like adding :

valid clearWhen(setup.debugMode)

one line after

NaxRiscv/src/main/scala/naxriscv/misc/PrivilegedPlugin.scala

Line 661 in fb12adc

}

would fix it.

But i didn't tested it.
Let me know it if fixes it for you.

. I'll make a PR if you think it's definitely a problem.

Thanks :D, PR welcome :)

Regards
Charles

[HaroldZ32]

Hi,

Looking at the code, seems like adding :

valid clearWhen(setup.debugMode)
one line after

NaxRiscv/src/main/scala/naxriscv/misc/PrivilegedPlugin.scala

Line 661 in fb12adc

}

would fix it.
But i didn't tested it. Let me know it if fixes it for you.

. I'll make a PR if you think it's definitely a problem.

Thanks :D, PR welcome :)

Regards Charles

Sorry for the late reply. This patch works on my testbench.

As an aside,I'll work for it(maybe Vexii as well) when I have free time. Should i make a PR for dcls(dual core lockstep) extension, or just create a new project for it?

[Dolu1990]

This patch works on my testbench.

Cool ^^

pushed on main.

Should i make a PR for dcls(dual core lockstep) extension, or just create a new project for it?

Hoo, how big is it of a change ?

[HaroldZ32]

Hoo, how big is it of a change ?

I need to extract all the ram and place it on the toplevel to compare the ram signal. It's not much code change but huge change of the architecture. Or is there a better way to do it?

[Dolu1990]

Ahhh, this sound painfull :D
There would be ways to automate this kind of transformations the SpinalHDL "netlist API", where basicaly, you can proceduraly transform / move things.
That is what is used for instance to automaticaly blackbox memories.