Inconsistencies Observed When Accessing Certain CSRs

[fly-1011]

Hello,
When testing NaxRiscv, I encountered several inconsistencies with Spike when accessing certain CSRs, such as cycle, instret, and mhpmevent.

The detailed log output is shown below:

cycle instret

*** MISSMATCH PC DUT=80001022 REF=80001000 ***

TIME=638
LAST PC COMMIT=80001022
INCOMING SPIKE PC=80001004

spike.log

core   0: 0x000000008000101a (0xc0089973) csrrw   s2, cycle, a7
core   0: exception trap_illegal_instruction, epc 0x000000008000101a
core   0:           tval 0x00000000c0089973
core   0: 0x0000000080001000 (0x343024f3) csrr    s1, mtval
core   0: 3 0x0000000080001000 (0x343024f3) x9  0x00000000c0089973
core   0: 0x0000000080001004 (0x341026f3) csrr    a3, mepc
core   0: 3 0x0000000080001004 (0x341026f3) x13 0x000000008000101a
core   0: 0x0000000080001008 (0x00000691) c.addi  a3, 4
core   0: 3 0x0000000080001008 (0x0691) x13 0x000000008000101e
core   0: 0x000000008000100a (0x34169073) csrw    mepc, a3
core   0: 3 0x000000008000100a (0x34169073) c833_mepc 0x000000008000101e
core   0: 0x000000008000100e (0x30200073) mret
core   0: 3 0x000000008000100e (0x30200073) c768_mstatus 0x0000000a007e008a
core   0: 0x000000008000101e (0xc0002973) csrr    s2, cycle
core   0: exception trap_illegal_instruction, epc 0x000000008000101e
core   0:           tval 0x00000000c0002973
core   0: 0x0000000080001000 (0x343024f3) csrr    s1, mtval
core   0: 3 0x0000000080001000 (0x343024f3) x9  0x00000000c0002973

mhpmevent10

*** MISSMATCH PC DUT=8000101e REF=80001000 ***

TIME=510
LAST PC COMMIT=8000101e
INCOMING SPIKE PC=80001004
ROB_ID=x8

core   0: 0x000000008000101a (0x32a89973) csrrw   s2, mhpmevent10, a7
core   0: exception trap_illegal_instruction, epc 0x000000008000101a
core   0:           tval 0x0000000032a89973
core   0: 0x0000000080001000 (0x343024f3) csrr    s1, mtval
core   0: 3 0x0000000080001000 (0x343024f3) x9  0x0000000032a89973

As shown in the logs above: Spike throws illegal instruction exceptions at csrr s2, cycle and csrr s2, instret, but NaxRiscv does not.

Additionally, Spike throws illegal instruction exceptions at csrrw s2, mhpmevent10, a7, but NaxRiscv does not. I checked the source code, and NaxRiscv does not define mhpmevent10.

NaxRiscv: commit 048b6c3