VCU118 2 GB memory or more

[XC1a]

Hi,
I am trying to support >1 GB memory for VCU118 board. To support this, I tried:
(1) Starting memory region at 0x4000_0000 and increase the size in litex target file o 0x8000_0000. But it failed, just as previous report that the starting address and the size should be aligned.
(2) Staring at 0x8000_0000 and move the io_regions in core.py to lower region, such as {0x4000_0000:0x4000_0000}. It can pass the check but it cannot generate the right bios and basically no output from uart.

After checking the address masking, it seems the io_region must stay in higher space. If you have some solutions to support at least 2GB memory?

Many thanks!

[Dolu1990]

Hi,
I litex, i'm realy not sure, i don't have any solution yet.

You used it with https://github.com/litex-hub/pythondata-cpu-naxriscv/blob/master/pythondata_cpu_naxriscv/verilog/configs/gen.scala ?

But it failed, just as previous report that the starting address and the size should be aligned

Which fail exactly ?

[XC1a]

Thanks for your reply. I will explain the details.

1. I found the link you shared is commited two month ago, I am still using the old version. I will update my version now. Then I will modify the 0xF0010000l to 0x40010000l and 0xF0C00000l to 0x40C00000l, with the beginning address of io_range being 0x40000000.
2. I also modified the 0xF0010000l and 0xF0C00000l in https://github.com/SpinalHDL/NaxRiscv/blob/main/src/main/scala/naxriscv/platform/litex/NaxSoc.scala
3. The board file is also modified to adjust the memory size to 0x80000000 (2GB).
4. Memory mapping region in https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/naxriscv/core.py also changes to new map.
   After trying that, I will update my results.
   Thanks again for your help!

[XC1a]

Oop, it still fails. The output of uart will be " __ ". It looks like it just gets stuck at the beginning of the bios output.

[XC1a]

This is current mapping:

def mem_map(self): # TODO
    return {
        "rom":      0x0000_0000,
        "sram":     0x1000_0000,
        "main_ram": 0x8000_0000,
        "csr":      0x4000_0000,
        "clint":    0x4001_0000,
        "plic":     0x40c0_0000,
    }

I also checked the folder and generated verilog, there is no stale "0xf0c00000".