about litex and dhrystone

[duanjiulon]

Hi,dear dolu,
I am currently learning how to use the kernel generated by Litex to run the dhrystone algorithm on SOC. The specific operation is: 1. Generate a SOC system with a Nax core, and then based on the dhrystone source code and simulation steps provided by you in your Naxriscv, set the starting address of the linker script to 0x0000000. This address is the address of the ROM or sram, which can run the program. However, once the drystone program is loaded, it freezes and cannot obtain the corresponding results in Verilator, May I ask why this is? Is it because I lack any environmental dependencies?

[Dolu1990]

Hi,

Which dhrystone software are you using, i don't remember providing any dhrystone for litex.
Did you ported the IO ?

[duanjiulon]

No,No,No,It's not about the dhrystone program for litex, but the dhrystone program and makefile in the ext/Maxsofware directory of your Naxriscv directory， 发自我的iPhone

…

------------------ Original ------------------ From: Dolu1990 ***@***.***> Date: Tue,Apr 30,2024 6:22 PM To: SpinalHDL/NaxRiscv ***@***.***> Cc: duanjiulon ***@***.***>, Author ***@***.***> Subject: Re: [SpinalHDL/NaxRiscv] about litex and dhrystone (Issue #96)

[Dolu1990]

but the dhrystone program and makefile in the ext/Maxsofware

No software from ext/NaxSoftware is designed to run on litex (excepted the instruction for debian)

[duanjiulon]

No software from ext/NaxSoftware is designed to run on litex (excepted the instruction for debian)

OK,fine,dear dolu,I have done this by litex intergration,
But his coremark performance is around 3.14. I would like to inquire about which key parameters need to be configured when configuring SOC parameters to achieve the best performance of nax_core, which is a coremark score of 5.02. Looking forward to your reply.！
in other words，

For the following configuration :

RV32IMASU, dual issue, OoO, linux compatible

64 bits fetch, 2 decode, 3 issue, 2 retire

Shared issue queue with 32 entries

Renaming with 64 physical registers

3 execution units (2*Int/Shift/branch, 1*load/store/mul/div/csr/env)

LSU with 16 load queue, 16 store queue

Load hit predictor (3 cycles load to use delay)

Store to load bypass

I$ 16KB/4W, D$ 16KB/4W 2 refill 2 writeback slots

MMU with ITLB 6 way/192 entries, DTLB 6 way/192 entries

BTB 1 way/512 entries, GSHARE 1 way/4KB, RAS 32 entries

I want to know about how to confige with the litex, agrument, thanks.

[Dolu1990]

Hi,

On litex, i generaly use :
python3 -m litex_boards.targets.digilent_nexys_video --cpu-type=naxriscv --bus-standard axi-lite --with-video-framebuffer --with-coherent-dma --with-sdcard --with-ethernet --xlen=64 --scala-args='rvc=true,rvf=true,rvd=true,alu-count=2,decode-count=2' --with-jtag-tap --sys-clk-freq 100000000 --cpu-count 2 --soc-json build/digilent_nexys_video/csr.json --update-repo no --load

to get a debian ready core, so you can change it with --xlen=32 and rvc=false,rvf=false,rvd=false

Then about coremark, it realy depend how you compiled it.
to get 5+ coremark, i used :
https://github.com/SpinalHDL/NaxSoftware/blob/main/baremetal/coremark/naxriscv_sim/core_portme.mak#L33

Also, with binary in the main memory, not in io mapped one.

I didn't tested on litex specificaly, that coremark was for simulation only.

[duanjiulon]

I didn't tested on litex specificaly, that coremark was for simulation only.

Hi，dear Dolu，

1. I would like to ask for some ideas about FetchCachePluginAXI4. scala here. Why is the Fetch interface directly divided into two types of axial interfaces: axial and axial, and what is its purpose

class FetchAxi4(ramDataWidth : Int,
                ioDataWidth : Int,
                toPeripheral : FetchL1Cmd => Bool
                ) extends Plugin{
  val logic = create late new Area{
    val cache = getService[FetchCachePlugin]
    val native = cache.mem.setAsDirectionLess

    val (ram, peripheral) = native.split(toPeripheral)
    val axiRam = master(ram.resizer(ramDataWidth).toAxi4())
    val axiPeripheral  = master(peripheral.resizer(ioDataWidth).toAxiLite4())

    Axi4SpecRenamer(axiRam)
    AxiLite4SpecRenamer(axiPeripheral)
  }
}

2.There is a setting in Briey.scala regarding ibus and dbus:

Val core=new Area{
Val config=VexRiscvConfig（
Plugins=cpuPlugins+=new DebugPlugin (debugClockDomain)
）

Val CPU=new VexRiscv (config)
Var iBus: Axi4ReadOnly=null
Var dBus: Axi4Shared=null
For (plugin<- config. plugins) plugin match{
Case plugin: IBusSimplePlugin=>iBus=plugin. iBus. toAxi4ReadOnly()
Case plugin: IBusCachedPlugin=>iBus=plugin. iBus. toAxi4ReadOnly()
Case plugin: DBusSimplePlugin=>dBus=plugin. dBus. toAxi4Shared()
Case plugin: DBusCachedPlugin=>dBus=plugin. dBus. toAxi4Shared (true)
Case plugin: CsrPlugin=>{
Plugin. externalInterrupt:=BufferCC (io. coreInterrupt)
Plugin. timerInterrupt:=timerCtrl. io. interrupt
}
Case plugin: DebugPlugin=>debugClockDomain{
ResetCtrl. axiReset setWhen (RegNext (plugin. io. resetOut))
Io. jtag<>plugin. io. bus. frmJtag()
}
Case_=>
}
}
```

What are the differences between the settings of ibus and dbus in the two types of cores
in the scala file：


````scala
 val core = new NaxRiscv(l)
    core.plugins.foreach{
      case p : FetchCachePlugin => iBus.bus << p.mem.toTilelink()
      case p : DataCachePlugin =>  dBus.bus << p.mem.toTilelink()
      case p : Lsu2Plugin => pBus.bus << p.peripheralBus.toTilelink()
      case p : PrivilegedPlugin => {
        p.io.int.machine.timer := mti.flag
        p.io.int.machine.software := msi.flag
        p.io.int.machine.external := mei.node.flag
        if(p.p.withSupervisor) p.io.int.supervisor.external := sei.node.flag
        if(p.p.withRdTime) p.io.rdtime := clint.thread.core.io.time
      }
      case _ =>
    }
  }
```

finally，I want to develop an Ibus and dbus interface similar to vex_core, but I don't know how to handle pbus

[Dolu1990]

Hi,

I would like to ask for some ideas about FetchCachePluginAXI4. scala here. Why is the Fetch interface directly divided into two types of axial interfaces: axial and axial, and what is its purpose

I think the reason was to be compatible with litex, but overall, a single bus is fine.

What are the differences between the settings of ibus and dbus in the two types of cores
in the scala file：

I'm not sure to understand, one is AXI one is tilelink, but fondamentaly the kind of access going through is the same, just that nax is writeback => less write trafic

but I don't know how to handle pbus

Would need a bridge.

But overall why not using the FetchAxi4 in the
val core = new NaxRiscv(l)
core.plugins.foreach{

?

I'm confused by the code above

[duanjiulon]

Would need a bridge.

There is currently no lib library available for converting pbus to AXI, and as far as I know, the LSUPlgins. scala file only has the axilite conversion interface.

I'm not sure to understand, one is AXI one is tilelink, but fondamentaly the kind of access going through is the same, just that nax is writeback => less write trafic

What I mean is the difference in functionality between FetchPlgins with AXI4 interface and ibus-axi4readonly in vex, and datacache-axi4 interface and vex-axi4dbus in vex

I'm confused by the code above

what you say is:

val core = new NaxRiscv(l)
    core.plugins.foreach{
      case p : FetchCachePlugin => iBus.bus << p.mem.toTilelink()
      case p : DataCachePlugin =>  dBus.bus << p.mem.toTilelink()
      case p : Lsu2Plugin => pBus.bus << p.peripheralBus.toTilelink()
      case p : PrivilegedPlugin => {
        p.io.int.machine.timer := mti.flag
        p.io.int.machine.software := msi.flag
        p.io.int.machine.external := mei.node.flag
        if(p.p.withSupervisor) p.io.int.supervisor.external := sei.node.flag
        if(p.p.withRdTime) p.io.rdtime := clint.thread.core.io.time
      }
      case _ =>
    }
  }

this one？
Because I only want a single core without the need for memory consistency, I currently want to change several buses to interface with Axi4

[duanjiulon]

dear dulo， in the gen.scala, I add the code:

plugins += new DataCacheAxi4(
      dataWidth = 32
    )
    plugins += new FetchAxi4(
      dataWidth = 32
    )
    ////
    plugins += new LsuPeripheralAxiLite4(
      ioDataWidth = 32
    )
    ////

I have modified fetchaxi4. scala to single port readonly axi4 and obtained the result. Can the three interfaces here be considered as ibus, dbus, and pbus。And I want to know the addressing range of the three buses in the core
thank you so much

output wire          FetchAxi4_logic_axi_arvalid,
  input  wire          FetchAxi4_logic_axi_arready,
  output wire [31:0]   FetchAxi4_logic_axi_araddr,
  output wire [7:0]    FetchAxi4_logic_axi_arlen,
  output wire [2:0]    FetchAxi4_logic_axi_arsize,
  output wire [1:0]    FetchAxi4_logic_axi_arburst,
  output wire [2:0]    FetchAxi4_logic_axi_arprot,
  input  wire          FetchAxi4_logic_axi_rvalid,
  output wire          FetchAxi4_logic_axi_rready,
  input  wire [31:0]   FetchAxi4_logic_axi_rdata,
  input  wire [1:0]    FetchAxi4_logic_axi_rresp,
  input  wire          FetchAxi4_logic_axi_rlast,
  output wire          DataCacheAxi4_logic_axi_awvalid,
  input  wire          DataCacheAxi4_logic_axi_awready,
  output wire [31:0]   DataCacheAxi4_logic_axi_awaddr,
  output wire [0:0]    DataCacheAxi4_logic_axi_awid,
  output wire [7:0]    DataCacheAxi4_logic_axi_awlen,
  output wire [2:0]    DataCacheAxi4_logic_axi_awsize,
  output wire [1:0]    DataCacheAxi4_logic_axi_awburst,
  output wire [2:0]    DataCacheAxi4_logic_axi_awprot,
  output wire          DataCacheAxi4_logic_axi_wvalid,
  input  wire          DataCacheAxi4_logic_axi_wready,
  output wire [31:0]   DataCacheAxi4_logic_axi_wdata,
  output wire [3:0]    DataCacheAxi4_logic_axi_wstrb,
  output wire          DataCacheAxi4_logic_axi_wlast,
  input  wire          DataCacheAxi4_logic_axi_bvalid,
  output wire          DataCacheAxi4_logic_axi_bready,
  input  wire [0:0]    DataCacheAxi4_logic_axi_bid,
  input  wire [1:0]    DataCacheAxi4_logic_axi_bresp,
  output wire          DataCacheAxi4_logic_axi_arvalid,
  input  wire          DataCacheAxi4_logic_axi_arready,
  output wire [31:0]   DataCacheAxi4_logic_axi_araddr,
  output wire [0:0]    DataCacheAxi4_logic_axi_arid,
  output wire [7:0]    DataCacheAxi4_logic_axi_arlen,
  output wire [2:0]    DataCacheAxi4_logic_axi_arsize,
  output wire [1:0]    DataCacheAxi4_logic_axi_arburst,
  output wire [2:0]    DataCacheAxi4_logic_axi_arprot,
  input  wire          DataCacheAxi4_logic_axi_rvalid,
  output wire          DataCacheAxi4_logic_axi_rready,
  input  wire [31:0]   DataCacheAxi4_logic_axi_rdata,
  input  wire [0:0]    DataCacheAxi4_logic_axi_rid,
  input  wire [1:0]    DataCacheAxi4_logic_axi_rresp,
  input  wire          DataCacheAxi4_logic_axi_rlast,
  input  wire          reset,
  output wire          LsuPeripheralAxiLite4_logic_axi_awvalid,
  input  wire          LsuPeripheralAxiLite4_logic_axi_awready,
  output wire [31:0]   LsuPeripheralAxiLite4_logic_axi_awaddr,
  output wire [2:0]    LsuPeripheralAxiLite4_logic_axi_awprot,
  output wire          LsuPeripheralAxiLite4_logic_axi_wvalid,
  input  wire          LsuPeripheralAxiLite4_logic_axi_wready,
  output wire [31:0]   LsuPeripheralAxiLite4_logic_axi_wdata,
  output wire [3:0]    LsuPeripheralAxiLite4_logic_axi_wstrb,
  input  wire          LsuPeripheralAxiLite4_logic_axi_bvalid,
  output wire          LsuPeripheralAxiLite4_logic_axi_bready,
  input  wire [1:0]    LsuPeripheralAxiLite4_logic_axi_bresp,
  output wire          LsuPeripheralAxiLite4_logic_axi_arvalid,
  input  wire          LsuPeripheralAxiLite4_logic_axi_arready,
  output wire [31:0]   LsuPeripheralAxiLite4_logic_axi_araddr,
  output wire [2:0]    LsuPeripheralAxiLite4_logic_axi_arprot,
  input  wire          LsuPeripheralAxiLite4_logic_axi_rvalid,
  output wire          LsuPeripheralAxiLite4_logic_axi_rready,
  input  wire [31:0]   LsuPeripheralAxiLite4_logic_axi_rdata,
  input  wire [1:0]    LsuPeripheralAxiLite4_logic_axi_rresp,

dear dulo，in the code，Can I directly understand it as a functional file for converting the original LsuPlugin_peripheralBus to a bridge of axi4lite?
There are a few things I don't quite understand here, reg_stage_cmd : Boolean = false,reg_stage_ret: Boolean = true， What is the reason for setting these two parameters to false and true respectively。

class LsuPeripheralAxiLite4(ioDataWidth : Int, 
                            reg_stage_cmd : Boolean = false,
                            reg_stage_ret: Boolean = true) extends Plugin{
  val logic = create late new Area{
    val peripheralBus = getServiceOption[LsuPlugin].map(_.peripheralBus).getOrElse(getServiceOption[Lsu2Plugin].map(_.peripheralBus).get)
    val native = peripheralBus.setAsDirectionLess
    val resized = native.resize(ioDataWidth)
    val axiRaw = resized.toAxiLite4()
    val axi = master(cloneOf(axiRaw))
    if (reg_stage_cmd) {
      axi.aw << axiRaw.aw.halfPipe()
      axi.w  << axiRaw.w.halfPipe()
      axi.ar << axiRaw.ar.halfPipe()
    } else {
      axi.aw << axiRaw.aw
      axi.w  << axiRaw.w
      axi.ar << axiRaw.ar
    }
    if (reg_stage_ret) {
      axi.b.halfPipe()  >> axiRaw.b
      axi.r.halfPipe()  >> axiRaw.r
    } else {
      axi.b  >> axiRaw.b
      axi.r  >> axiRaw.r
    }
    AxiLite4SpecRenamer(axi)
  }
}

[duanjiulon]

Hello, dear dulo,recently I tested multiple core configurations of naxriscv in your recommended emulation method (on git) emulation and litex separately, and found that for the first way: loading the elf file into a specific sim_mem for testing will have better results, 2-alu, 2-decode will have a dhrystone score of 2.93, but under the same configuration, I use litex_ SoC loading ROM for simulation or board testing, the result is only about 1 drystone score,please help me why is this,thanks

[Dolu1990]

Hi,
Could you send me the fst wave of the litex simulation ?

[duanjiulon]

Hi，dear Dolu，Considering that I often use the suffix vcd file to analyze waveforms, and the fst wave file cannot be opened correctly on my computer, I have sent you the. vcd file and fst file together. The program flow of dhrystone is as follows: 1. Print version information to the serial port, you can check reslutREADME.txt, then read the start time, start running dhrystone, read the end time, and print the result to the serial port after running. The compressed file size may be around 2GB, please be patient and download it. Thank you for your suppor！ https://mail.qq.com/cgi-bin/ftnExs_download?k=25343463c6aaba420053485e1264061c1c400007515505554902015b064902515c0719525601511e01510400575705020151555634683455174014145512511d1e5d446309&t=exs_ftn_download&code=d44c4d43 段玖龙 ***@***.***  

…

------------------ 原始邮件 ------------------ 发件人: "SpinalHDL/NaxRiscv" ***@***.***>; 发送时间: 2024年6月5日(星期三) 晚上10:11 ***@***.***>; ***@***.******@***.***>; 主题: Re: [SpinalHDL/NaxRiscv] about litex and dhrystone (Issue #96) Hi, Could you send me the fst wave of the litex simulation ? — Reply to this email directly, view it on GitHub, or unsubscribe. You are receiving this because you authored the thread.Message ID: ***@***.***> 从QQ邮箱发来的超大附件 fst wave.zip (2.23G, 2024年07月06日 11:08 到期)进入下载页面：https://mail.qq.com/cgi-bin/ftnExs_download?k=25343463c6aaba420053485e1264061c1c400007515505554902015b064902515c0719525601511e01510400575705020151555634683455174014145512511d1e5d446309&t=exs_ftn_download&code=d44c4d43

[duanjiulon]

dear dulo,I'm sorry to ask you another question. If I still want to get a lightweight core, which plugins do I need to close while ensuring that the core can run? For example, can branch prediction be closed? Can many random launches be achieved by turning off certain piungis and turning them into sequential launches, resulting in a core that occupies less LUT resources (similar to vex_core)，thank you so much！

[Dolu1990]

Hi,

I checked the simulation wave, and i can see the the integer divider is never used, did you compiled with -march=rv32im ?

[Dolu1990]

which plugins do I need to close while ensuring that the core can run?

You may remove the PerformanceCounterPlugin, reduce the LQ SQ size and swap the MMU for the StaticAddressTranslationPlugin, ensure the core if configure with single decoder, 1 alu, no RVC

Also, you may be interrested by VexiiRiscv is you look for small 64 bits support, but in order.