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msgid"The ``Bool`` type corresponds to a boolean value (True or False) or a single bit/wire used in a hardware design. While named similarly it should not be confused with Scala `Boolean` type which does not describe hardware but truth values in the Scala generator code."
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msgid"The ``Bool`` type corresponds to a boolean value (True or False) or a single bit/signal used in a hardware design. While named similarly it should not be confused with Scala `Boolean` type which does not describe hardware but truth values in the Scala generator code."
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#: ../../SpinalHDL/Data types/bool.rst:14
@@ -77,7 +77,7 @@ msgid "The signal direction of assignment operators `:=` is managed by SpinalHDL
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#: ../../SpinalHDL/Data types/bool.rst:37
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msgid"Multiple uses of the assignment operator are allowed, such that it is normal for a signal wire to act as a source (provides a value to drive HDL state) to be able to connect and drive multiple inputs of other HDL constructs. When a Bool instance used as a source the order the assignment statements appear or are executed in Scala does not matter, unlike when it is used as a sink (captures state)."
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msgid"Multiple uses of the assignment operator are allowed, such that it is normal for a signal to act as a source (provides a value to drive HDL state) to be able to connect and drive multiple inputs of other HDL constructs. When a Bool instance used as a source the order the assignment statements appear or are executed in Scala does not matter, unlike when it is used as a sink (captures state)."
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#: ../../SpinalHDL/Data types/bool.rst:44
@@ -271,7 +271,7 @@ msgid "All edge detection functions will instantiate an additional register via
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#: ../../SpinalHDL/Data types/bool.rst:178
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msgid"This feature does not reconfigure a D-type Flip-Flop to use an alternative CLK source, it uses two D-type Flip-Flop in series chain (with both CLK pins inheriting the default ClockDomain). It has combinational logic to perform edge detection based on the output Q states."
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msgid"This feature does not reconfigure a D-type flip-flop to use an alternative CLK source, it uses two D-type flip-flop in series chain (with both CLK pins inheriting the default ClockDomain). It has combinational logic to perform edge detection based on the output Q states."
msgid"Note the line ``import $file.^.SpinalHDL.build``. It is using ammonite REPL magic ``$file`` to look up the ``build.sc`` of SpinalHDL. (The ``^`` moves up one directory from the current.) This is assuming the following directory structure:"
msgid"Note the addition to ``scalacOptions``. Without it, compiling any Spinal project might produce countless ``SCOPE VIOLATION`` or ``HIERARCHY VIOLATION`` errors because the ``idslplugin`` of spinal is not actually invoked."
msgid"After the changes, the next compilation of your project will take a considerable amount of time (~2 minutes). This is only for the first compile. After this, your project should compile as usual."
#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:82
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msgid"In VHDL, every time you want to define a bunch of registers, you need the carry the clock and the reset wire to them. In addition, you have to hardcode everywhere how those clock and reset signals should be used (clock edge, reset polarity, reset nature (async, sync))."
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msgid"In VHDL, every time you want to define a bunch of registers, you need the carry the clock and the reset signal to them. In addition, you have to hardcode everywhere how those clock and reset signals should be used (clock edge, reset polarity, reset nature (async, sync))."
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#: ../../SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.rst:84
@@ -173,19 +173,19 @@ msgid "This is sufficient for generating hardware. For simulation continue with
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#: ../../SpinalHDL/Getting Started/Install and setup.rst:149
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msgid"An All-in-One solution offered by SpinalHDL maintainer `Readon <https://github.com/Readon>` is available to install and run SpinalHDL with Verilator simulation and formal verification via SymbiYosys. Download `it <https://github.com/Readon/msys2-installer/releases>`__ and install the environment anywhere on your disk. Start the build environment by clicking on the MSYS2-MINGW64 icon in the Start menu and use the MSYS2 default console. An alternative is to use the Windows Terminal or a Tabby-like application and use the startup command ``%MSYS2_ROOT%\\msys2_shell.cmd -defterm -here -no-start -mingw64``, where the ``%MSYS2_ROOT%`` is the location of the msys2 installation. It is worth noting that if you want to use it offline, you should carefully select the libraries that the project depends on, otherwise you will need to download the packages manually. See the README for the repos for more details."
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msgid"An All-in-One solution offered by SpinalHDL maintainer `Readon <https://github.com/Readon>`_ is available to install and run SpinalHDL with Verilator simulation and formal verification via SymbiYosys. Download `it <https://github.com/Readon/msys2-installer/releases>`__ and install the environment anywhere on your disk. Start the build environment by clicking on the MSYS2-MINGW64 icon in the Start menu and use the MSYS2 default console. An alternative is to use the Windows Terminal or a Tabby-like application and use the startup command ``%MSYS2_ROOT%\\msys2_shell.cmd -defterm -here -no-start -mingw64``, where the ``%MSYS2_ROOT%`` is the location of the msys2 installation. It is worth noting that if you want to use it offline, you should carefully select the libraries that the project depends on, otherwise you will need to download the packages manually. See the README for the repos for more details."
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#: ../../SpinalHDL/Getting Started/Install and setup.rst:158
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msgid"MSYS2 verilator for simulation"
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#: ../../SpinalHDL/Getting Started/Install and setup.rst:160
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msgid"We recommend to install compiler/verilator through `MSYS2 <https://www.msys2.org>`. Other methods of installing gcc/make/shell (e.g. chocolatey, scoop, etc.) may also work but are untested."
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msgid"We recommend to install compiler/verilator through `MSYS2 <https://www.msys2.org>`_. Other methods of installing gcc/make/shell (e.g. chocolatey, scoop, etc.) may also work but are untested."
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#: ../../SpinalHDL/Getting Started/Install and setup.rst:163
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msgid"SpinalHDL maintainer `Readon <https://github.com/Readon>` is maintaining a MSYS2 fork that default installs all needed officially available and custom built packages (also maintained by Readon `here <https://github.com/Readon/MINGW-SpinalHDL>`) for simulation and formal verification. It can be found `here <https://github.com/Readon/msys2-installer>`. If used then the packages installed below via ``pacman`` are already installed and those installation steps can be skipped."
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msgid"SpinalHDL maintainer `Readon <https://github.com/Readon>`_ is maintaining a MSYS2 fork that default installs all needed officially available and custom built packages (also maintained by Readon `here <https://github.com/Readon/MINGW-SpinalHDL>`__) for simulation and formal verification. It can be found `here <https://github.com/Readon/msys2-installer>`__. If used then the packages installed below via ``pacman`` are already installed and those installation steps can be skipped."
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#: ../../SpinalHDL/Getting Started/Install and setup.rst:169
@@ -209,7 +209,7 @@ msgid "MSYS2 for formal verification"
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#: ../../SpinalHDL/Getting Started/Install and setup.rst:198
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msgid"In addition to the steps above we also need to install yosys, sby, z3 and yices. Both yosys(yosys-smtbmc workable) and sby are not available as official MSYS2 packages, but packages are provided by `Readon <https://github.com/Readon>`. If you used their installer then these steps are not needed (you should check if there are newer packages available)."
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msgid"In addition to the steps above we also need to install yosys, sby, z3 and yices. Both yosys(yosys-smtbmc workable) and sby are not available as official MSYS2 packages, but packages are provided by `Readon <https://github.com/Readon>`_. If you used their installer then these steps are not needed (you should check if there are newer packages available)."
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#: ../../SpinalHDL/Getting Started/Install and setup.rst:212
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