Scope docs to only facilities used outside SpinalHDL/SpinalHDL: remove StreamAccessibleFifo, StreamShiftChain, PackedBundle page, and undocumented BusSlaveFactory methods

Co-authored-by: Readon <3614708+Readon@users.noreply.github.com>

Author: Copilot

source/SpinalHDL/Libraries/bus_slave_factory.rst

@@ -94,50 +94,5 @@ Functionality
      - T
      - | Set bits of ``that`` when the corresponding write bit is ``1``.
        | Writing a ``1`` to a bit position sets that bit; writing ``0`` has no effect.
-   * - clearOnSet(that,address,bitOffset)
-     - T
-     - | Clear bits of ``that`` when the corresponding write bit is ``1``.
-       | Writing a ``1`` to a bit position clears that bit; writing ``0`` has no effect.
-   * - readAndSetOnSet(that,address,bitOffset)
-     - T
-     - Map ``that`` as readable at ``address`` and apply the ``setOnSet`` behaviour on write
-   * - readAndClearOnSet(that,address,bitOffset)
-     - T
-     - Map ``that`` as readable at ``address`` and apply the ``clearOnSet`` behaviour on write
-   * - createReadAndSetOnSet(dataType,address,bitOffset)
-     - T
-     - Create a register of ``dataType``, make it readable at ``address``, and apply the ``setOnSet`` behaviour on write
-   * - createReadAndClearOnSet(dataType,address,bitOffset)
-     - T
-     - Create a register of ``dataType``, make it readable at ``address``, and apply the ``clearOnSet`` behaviour on write
-   * - createReadMultiWord(that,address)
-     - T
-     - | Create a register initialised from ``that``, and map it as a multi-word read starting at ``address``.
-       | Extends across consecutive addresses when ``that`` is wider than one bus word.
-   * - createWriteMultiWord(that,address)
-     - T
-     - | Create a register initialised from ``that``, and map it as a multi-word write starting at ``address``.
-       | Extends across consecutive addresses when ``that`` is wider than one bus word.
-   * - createWriteAndReadMultiWord(that,address)
-     - T
-     - | Create a register initialised from ``that``, and map it as both readable and writable across multiple words starting at ``address``.
-   * - multiCycleRead(address,cycles)
-     - Unit
-     - | Insert a read latency of ``cycles`` bus clock cycles for accesses to ``address``.
-       | Useful when the read data requires more than one cycle to become available (e.g. synchronous RAM reads).
-   * - readSyncMemWordAligned(mem,addressOffset,bitOffset,memOffset)
-     - Mem[T]
-     - | Memory-map a synchronous-read ``Mem`` at ``addressOffset`` for word-aligned bus access.
-       | Each bus word corresponds to one memory word. Automatically inserts a 2-cycle read latency.
-   * - readSyncMemMultiWord(mem,addressOffset,memOffset)
-     - Mem[T]
-     - | Memory-map a synchronous-read ``Mem`` at ``addressOffset`` when each memory element spans multiple bus words.
-       | Automatically inserts a 2-cycle read latency.
-   * - writeMemWordAligned(mem,addressOffset,bitOffset,memOffset)
-     - Mem[T]
-     - Memory-map a ``Mem`` for word-aligned bus write access at ``addressOffset``. Supports byte-enable masks when available.
-   * - writeMemMultiWord(mem,addressOffset)
-     - Mem[T]
-     - | Memory-map a ``Mem`` at ``addressOffset`` for write access when each memory element spans multiple bus words.
-       | The memory element width must be a multiple of the bus data width.
+
 

source/SpinalHDL/Libraries/index.rst

@@ -32,7 +32,6 @@ To use features introduced in followings chapter you need, in most of cases, to
    fiber
    binarySystem
    regIf
-   packed_bundle
    Bus/index
    Com/index
    IO/index

source/SpinalHDL/Libraries/packed_bundle.rst

@@ -610,86 +610,6 @@ You can apply them by calling the corresponding method on a ``Stream`` or by pas
    val pipeType: StreamPipe = StreamPipe.M2S
    sink << pipeType(source)
 
-StreamAccessibleFifo
-^^^^^^^^^^^^^^^^^^^^
-
-``StreamAccessibleFifo`` is a FIFO where all stored elements are accessible at any time through the ``io.states`` ports in addition to the normal ``push``/``pop`` stream interface.
-This is useful when logic needs to inspect the entire contents of the queue without consuming elements.
-
-.. list-table::
-   :header-rows: 1
-   :widths: 2 2 5
-
-   * - Signal
-     - Type
-     - Description
-   * - ``io.push``
-     - slave Stream[T]
-     - Input stream; pushes data into the FIFO
-   * - ``io.pop``
-     - master Stream[T]
-     - Output stream; pops data from the FIFO
-   * - ``io.states``
-     - Vec(master Flow[T], length)
-     - Read-only view of each slot in the FIFO
-
-.. code-block:: scala
-
-   val input  = Stream(Bits(8 bits))
-   val output = Stream(Bits(8 bits))
-
-   // Instantiate a StreamAccessibleFifo with 4 slots
-   val fifo = StreamAccessibleFifo(input, output, length = 4)
-
-   // Access the first slot's data without consuming it
-   when(fifo.io.states(0).valid) {
-     val firstElement = fifo.io.states(0).payload
-   }
-
-StreamShiftChain
-^^^^^^^^^^^^^^^^
-
-``StreamShiftChain`` is a shift-register chain of ``length`` registered stream stages.
-Each stage is a ``m2sPipe`` of the previous one.
-The ``io.states`` ports expose all intermediate stages as ``Flow``\s so that any stage can be inspected.
-An optional ``io.clear`` input can flush all stages simultaneously.
-
-.. list-table::
-   :header-rows: 1
-   :widths: 2 2 5
-
-   * - Signal
-     - Type
-     - Description
-   * - ``io.push``
-     - slave Stream[T]
-     - Input stream; enters the first stage of the chain
-   * - ``io.pop``
-     - master Stream[T]
-     - Output stream; exits the last stage of the chain
-   * - ``io.states``
-     - Vec(master Flow[T], length)
-     - Read-only view of each registered stage in the chain
-   * - ``io.clear``
-     - in Bool (default False)
-     - When asserted, flushes all pipeline stages
-
-.. code-block:: scala
-
-   val input  = Stream(Bits(8 bits))
-   val output = Stream(Bits(8 bits))
-
-   // Create a 3-stage shift chain
-   val chain = StreamShiftChain(input, output, length = 3)
-
-   // Read the second stage value without consuming it
-   when(chain.io.states(1).valid) {
-     val stage1Data = chain.io.states(1).payload
-   }
-
-   // Flush all stages
-   chain.io.clear := flushCondition
-
 StreamTransactionExtender
 ^^^^^^^^^^^^^^^^^^^^^^^^^